电工技术学报  2023, Vol. 38 Issue (18): 4947-4962    DOI: 10.19595/j.cnki.1000-6753.tces.221214
电力电子 |
碳化硅功率模块封装技术综述
王来利, 赵成, 张彤宇, 闫飞飞
电力设备电气绝缘国家重点实验室(西安交通大学) 西安 710049
Review of Packaging Technology for Silicon Carbide Power Modules
Wang Laili, Zhao Cheng, Zhang Tongyu, Yan Feifei
School of Electrical Engineering Xi’an Jiaotong University Xi’an 710049 China
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摘要 碳化硅作为宽禁带半导体的代表,理论上具有极其优异的性能,有望在大功率电力电子变换器中替换传统硅IGBT,进而大幅提升变换器的效率以及功率密度等性能。但是目前商用碳化硅功率模块仍然沿用传统硅IGBT模块的封装技术,且面临着高频寄生参数大、散热能力不足、耐温低、绝缘强度不足等问题,限制了碳化硅半导体优良性能的发挥。为了解决上述问题,充分发挥碳化硅芯片潜在的巨大优势,近年来出现了许多针对碳化硅功率模块的新型封装技术和方案,重点关注碳化硅功率模块封装中面临的电、热以及绝缘方面的挑战。该文从优化设计方法所依据的基本原理出发,对各种优化技术进行分类总结,涵盖了降低高频寄生电感、增强散热性能、提高耐高温能力以及提升绝缘强度的一系列相关技术。在此基础上,对相关的可靠性问题进行总结。最后基于碳化硅功率模块封装技术的现状,对相关技术的未来发展进行了展望。
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王来利
赵成
张彤宇
闫飞飞
关键词 碳化硅功率模块寄生电感散热能力耐高温能力绝缘能力可靠性    
Abstract:Silicon carbide MOSFETs are of excellent performance and potentially replace traditional silicon IGBTs in high-power power converters. However, commercial silicon carbide power modules still employ the packaging technology of traditional silicon IGBT modules, limiting the excellent performances of silicon carbide semiconductors. In order to solve the above problem and take advantage of silicon carbide chips, many new packaging schemes for silicon carbide power modules have emerged in recent years, focusing on the electrical, thermal, and insulation challenges in the packaging of silicon carbide power modules.
As for the electrical challenges, the parasitic inductance in commutation loops is widely concerned. The parasitic inductance on the conductors connects the chips to the external circuits in power modules, which can greatly affect the switching performance of silicon carbide MOSFETs, such as increasing voltage overshoot and arousing oscillations. Then the stress on the chip will be increased, and the switching losses may also be enlarged. Compared to Si IGBTs, SiC MOSFET-based power modules can switch faster, which presents more strict requirements for parasitic inductance. Therefore, new packaging structures are demanded to lower parasitic inductance. There are two ways. The first one is to reduce the self-parasitic inductance. In this aspect, the shapes of connection conductors are optimized. The ribbon bonding techniques, such as aluminum ribbons, copper ribbons, and aluminum-copper ribbons, aim to mitigate the parasitic inductance by increasing the cross-sectional areas. Accordingly, the self-parasitic inductance can be well reduced. Similar techniques include copper-clip connections and planar connections. The second way adopts loop mutual inductance to eliminate the overall parasitic inductance. By reducing the areas of commutation loops, the mutual inductance between conductors can be greatly increased, which can reduce self-parasitic inductance and then reduce the overall parasitic inductance.
As for the thermal challenges, there are two problems. On the one hand, the overall package size must be reduced to minimize parasitic inductance, making the heat dissipation issues more severe. Many methods have been proposed to enhance heat dissipation in limited spaces. The optimization of heat dissipation is mainly attributed to two technical routes: shortening the heat transfer paths and increasing the heat transfer areas. To shorten heat transfer paths, some modules remove the baseplates and even directly solder the substrates on the heatsinks. The key to improving equivalent heat dissipation areas on the bottom surface of the chip is to achieve a uniform temperature distribution. Some research has realized this goal by changing the material of the copper layer under the chip or integrating heat pipes into baseplates or substrates. In addition, double-side cooling structures can be utilized to directly increase equivalent heat transfer areas. On the other hand, the ability of silicon carbide chips to operate at high temperatures is limited by the shortcomings of traditional packaging materials. The reliability of current high-temperature-resistant packaging materials requires further verification under a wide range of temperature cycles.
As for insulation challenges, high voltage variation slews and high electric field strength in power modules place higher demands on the insulation performance of the package. Methods to enhance insulation performances in compact spaces of power modules have been reported, such as employing stacked substrates, optimizing three-phase point structures, and adopting functional gradient materials.
The packaging technology of SiC power modules is reviewed from aspects of lowering parasitic inductance, enhancing thermal performance, and improving insulation performance. Rules for optimizing the performance of SiC power modules on the three aspects are summarized.
Key wordsSilicon carbide power modules    parasitic inductance    heat dissipation capability    high temperature resistance    insulation capability    reliability   
收稿日期: 2022-06-24     
PACS: TN305  
  TM46  
基金资助:国家重点研发计划资助项目(2019YFE0122800)
通讯作者: 王来利,男,1982年生,教授,博士生导师,研究方向为电力电子封装集成。E-mail: llwang@mail.xjtu.edu.cn   
作者简介: 赵成,男,1996年生,博士研究生,研究方向为电力电子封装集成。E-mail: zhaocheng3117@stu.xjtu.edu.cn
引用本文:   
王来利, 赵成, 张彤宇, 闫飞飞. 碳化硅功率模块封装技术综述[J]. 电工技术学报, 2023, 38(18): 4947-4962. Wang Laili, Zhao Cheng, Zhang Tongyu, Yan Feifei. Review of Packaging Technology for Silicon Carbide Power Modules. Transactions of China Electrotechnical Society, 2023, 38(18): 4947-4962.
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