The Current Balance Analysis and Optimization Design of the Laminated Busbar with Discrete Devices in Parallel
Yu Shaolin1, Zhang Xing1, Wang Jianing1,2, Zhou Weinan1, Huang Yaodong1
1. National and local Joint Engineering Laboratory for Renewable Energy Access to Grid Technology Hefei University of Technology Hefei 230009 China; 2. Institute of Energy Hefei Comprehensive National Science Center Hefei 230088 China
Abstract：To accommodate high-power power conversion application scenarios, the SiC MOSFETs must be used in parallel. In medium and high-power inverters, the laminated busbar with low parasitic inductance characteristics is usually used as an interconnection structure for DC-link capacitors and power devices. An asymmetrical laminated busbar structure can lead to asymmetrical parasitic parameters, which in turn causes unbalanced current distribution among the parallel devices. Therefore, in addition to the low parasitic inductance, the symmetry of the parasitic parameter for each parallel branch is a critical design factor for the laminated busbar with discrete devices in parallel. This paper analyzed the current sharing performance of the laminated busbar with six discrete devices in parallel and further optimized the busbar structure. Firstly, the equivalent parasitic parameters of each parallel branch of the original laminated busbar are extracted by the established parasitic parameter model. The results show that the equivalent parasitic inductance and parasitic resistance of each parallel branch are unbalanced in the static process. The effect of the unbalanced parasitic parameters on the current distribution among the paralleled devices is analyzed by the established double-pulse simulation circuit. It is shown that reducing the switching speed can weaken the effect of the parasitic inductance variability on the dynamic current imbalance. In the context of large-load applications, it is necessary to pay more attention to the effect of parasitic resistance differences on the static current imbalance. Then, aiming at the extraction accuracy of the static parasitic parameters for the laminated busbar with discrete devices in parallel, this paper proposes a sink location method. It points out that the current sink should be the maximum point of the aggregated current, while the impedance after the point does not affect the current distribution. Based on this principle, the real sink point in the AC busbar is located in combination with the finite simulation software, which improves the extraction accuracy of static parasitic parameters. In addition, the mutual coupling effect on the parasitic parameters of the laminated busbar is explored. It is found that the presence of coupled mutual inductance will make it possible for the equivalent parasitic parameters of asymmetric parallel branches to be consistent. The original laminated busbar with six discrete devices in parallel is then optimized. By adjusting the position of the current sink point, thus matching the self-inductance and mutual inductance, the parasitic parameters of the parallel branch can be equalized. The parasitic parameters of the optimized laminated bus are extracted, and the results show that the parasitic parameters of each parallel branch are more balanced in the static process. Finally, a double-pulse test platform was built to test the static currents of each parallel device of the optimized laminated busbar. Compared with the original laminated busbar, the experimental results show that the static unbalanced current has been greatly improved.
於少林, 张兴, 王佳宁, 周伟男, 黄耀东. 分立器件并联型叠层母排均流分析及优化设计[J]. 电工技术学报, 2023, 38(8): 2086-2099.
Yu Shaolin, Zhang Xing, Wang Jianing, Zhou Weinan, Huang Yaodong. The Current Balance Analysis and Optimization Design of the Laminated Busbar with Discrete Devices in Parallel. Transactions of China Electrotechnical Society, 2023, 38(8): 2086-2099.
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2023, Vol. 38 
