Abstract：With the development of distributed generation technology and the growth of DC loads, DC distribution networks have regained significant attention from scholars worldwide. Due to their inherently low impedance characteristics, short-circuit faults can generate fault currents with high magnitude, high-speed rates of change, and no natural zero-crossing points, seriously compromising system stability. With the rapid advancement of wide bandgap semiconductor technology, solid-state circuit breakers (SSCBs) based on silicon carbide (SiC) power devices have demonstrated great application potential in the protection of medium- and low-voltage DC distribution networks. These devices offer advantages such as fast response, high voltage withstand capability, low on-state resistance, arc-free interruption, and excellent thermal stability. However, during the high-speed interruption of short-circuit faults, strong coupling between the parasitic parameters of the main circuit and the inherent characteristics of SiC devices often gives rise to voltage and current oscillations. Such oscillations can not only compromise system operational stability and protection coordination but also pose a threat to the overall security of the DC grid. Therefore, this paper examines methods for suppressing oscillation amplitudes in solid-state circuit breakers using SiC JFET devices under fault conditions. Firstly, a medium-voltage DC SiC SSCB topology based on series-connected normally-on SiC JFETs is proposed. The influence patterns of parasitic parameters on voltage/current oscillations are investigated, revealing the oscillation mechanism caused by the coupling between intrinsic SiC JFET parameters and parasitic components. Secondly, a small-signal model considering device nonlinear characteristics is established based on the dynamic impedance characteristics of the SiC JFET-based SSCB. By deriving the closed-loop transfer function and applying the generalized Nyquist stability criterion, the instability mechanism of SiC SSCB under the interaction of parasitic parameters and snubber circuits is revealed. Accordingly, a stability enhancement method for SiC SSCB is proposed. Finally, a 1.5 kV/63 A medium-voltage DC SiC SSCB prototype is developed. Experimental comparisons of interruption characteristics before and after optimization under short-circuit conditions demonstrate that the optimized SiC SSCB achieves reliable fault interruption. It effectively suppresses voltage/current oscillations during the interruption process, thereby enhancing system stability and safety. The following conclusions are drawn. (1) The coupling of parasitic parameters within normally-on SiC JFET devices and the busbars is the primary cause of voltage oscillations. Mismatches in these parasitic parameters lead to uneven energy distribution among cascaded devices during fault interruption, thereby inducing voltage self-oscillations that affect system stability. (2) Adding parallel capacitors to the gate-source terminals of cascaded devices can effectively reduce the amplitude of voltage oscillations and significantly improve the system's stability margin. (3) Under the premise that the fault response time remains essentially unchanged, correctly selecting the gate-source parallel capacitor can effectively reduce the peak drain-source oscillations at the moment of device turn-off in cascaded devices. As a result, good dynamic and static voltage balancing is achieved, and gate-source voltage overshoot is suppressed.
何东, 王振忠, 蒋磊, 兰征, 曾进辉. 基于常通型SiC JFET器件级联的中压直流固态断路器振荡稳定性分析及提升方法[J]. 电工技术学报, 2026, 41(8): 2627-2640.
He Dong, Wang Zhenzhong, Jiang Lei, Lan Zheng, Zeng Jinhui. Analysis and Enhancement Methods for Oscillation Stability in Medium-Voltage DC SSCB Based on Cascaded Normally-on SiC JFET. Transactions of China Electrotechnical Society, 2026, 41(8): 2627-2640.
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