Single-Phase Bridgeless Voltage-Doubler Power Factor Correction Converterswith Shared Components
Ding Mingyuan1, Li Haoyu1, Zhao Lei1, Ben Hongqi1, Wang Zhiliang2
1. School of Electrical Engineering and Automation Harbin Institute of Technology Harbin 150001 China; 2. Beijing Electro-mechanical Engineering Institute Beijing 100074 China
Abstract：Power factor and efficiency are important technical requirements for the front-end power factor correction (PFC) converters in avionic power systems with 400 Hz line frequency. Optimizing the topology structure can fundamentally improve and enhance the performance of the PFC converter. As a consequence, this paper proposes a family of single-phase bridgeless voltage-doubler PFC topologies to achieve the component sharing of dual-converter cells. Based on the Sepic/Cuk/Zeta-type dual-converter bridgeless PFC topologies, the current path of the intermediate-storage unit is reconstructed by adopting the bidirectional switches and half-bridge output structure. Hence, the combination of dual-converter cells is achieved. Among them, the semiconductor type of half-bridge structure is determined by the current polarity. The switches are utilized when the flowing current is bidirectional, and the diodes simplify the control scheme when the flowing current is unidirectional. The working principle of the circuit remains unchanged after sharing the components, and the merits of high power factor and low voltage stress are fully retained. Compared with other bridgeless Sepic/Cuk/Zeta-type PFC topologies, the number of filter inductors, energy-storage inductors, and energy-storage capacitors is minimized, improving the component utilization. The voltage stresses of the switches are greatly reduced by adopting the voltage-doubler output structure. Moreover, the DC output voltage polarity of the Cuk-type topology is positive, thus improving the performance of the circuit. Considering the similarity of principle analysis, the proposed Sepic-type bridgeless voltage-doubler PFC converter is analyzed as an example. Similarly, the other converters of the proposed family can be analyzed. The energy-storage inductor processes three working stages during a switching cycle, and the common set of the energy-storage capacitor and inductor operates for both positive and negative half-line cycles. The expression of input current can be obtained based on the input-output instantaneous power balance. It is worth noting that the input current is naturally in phase with the input voltage in discontinuous conduction mode (DCM) when the parallel inductance, duty cycle, and switching frequency are fixed. The static gain of the proposed converter is defined by the ratio between the DC output voltage and the root-mean-square (rms) value of the input voltage, which can be regulated flexibly by adjusting the duty cycle. Thus, the proposed converter only requires a control loop for the output voltage. The crossover frequency of the voltage compensator is designed well below twice the line frequency to attenuate excessive second-harmonic injection from output voltage into the duty cycle. The pulse width modulation (PWM) signal modulator generates control signals to drive the bidirectional switches. During the positive or negative half-line cycle of the AC input voltage, the duty cycle control signal is applied to the main switch, and the other switch is always turned on to reduce its loss. A Sepic-type experimental prototype has been constructed to verify the proposed topology. The proposed converter with 400 Hz input voltage has a maximum efficiency of 95.9% and a current THD of 3.5% with an almost unity power factor.
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2025, Vol. 40 
