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| Impact of Chip Parameter Variability on the Thermal Safe Operating Area of Multi-Chip Parallel SiC MOSFETs |
| Jiang Xinyu1,2, Sun Peng1, Tang Xinling2, Jin Rui2, Zhao Zhibin1,2 |
1. State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources North China Electric Power University Beijing 102206 China;
2. Beijing Institute of Smart Energy Beijing 102209 China |
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Abstract SiC MOSFET power modules typically utilize parallel chip configurations to meet high-current demands in power electronic systems. However, inherent variations in the fabrication process cause chip parameter variability, which, along with the asymmetric package parasitic, uneven thermal resistance, and cross-chip thermal coupling within conventional module designs, creates significant electro-thermal (ET) imbalance among paralleled chips. It leads to divergent operational boundaries under specific temperature constraints at the junction. This paper proposes a thermal safe operation area (TSOA) assessment methodology for multi-chip paralleled power modules, investigating the impact of chip parameter variability on the TSOA through Monte Carlo simulations. A solution to expand TSOA is devised.
Firstly, ET co-simulation, spanning from chip-level to system-level, is combined with an output current prediction model, defined as the output capacity when the junction temperature of the hottest chip reaches thermal constraints. A simplified EKV model and a 2D thermal network model are used to analyze the ET behavior of a multi-chip parallel power module. ET simulations of its application circuit (e.g., buck converter) under different output currents predict the junction temperature of each chip. Then, a four-parameter model is developed to describe the relationship between junction temperature and output current. This ET- simulation-based approach addresses the analytical challenges posed by the asymmetric package parasitic, uneven thermal resistance, and inter-chip thermal coupling. Compared to traditional stepwise calculation for output current limits, this method determines TSOA more efficiently with just three ET simulations. The ET model is validated by the double pulse test experiment, exhibiting a discrepancy of less than 9% in switching loss prediction for two paralleled chips. The output current prediction model is further verified by stepwise ET simulation, achieving a 1.5% error in output current boundary estimation.
Secondly, Monte Carlo (MC) simulations are employed to analyze the impact of chip parameter variability on TSOA under various thermal constraints, ranges, and switching frequencies. The analysis quantifies frequency-dependent sensitivity to parameter variations and suggests a solution to expand TSOA. MC simulations are conducted to identify a variation threshold that keeps the overall TSOA reduction rate (β) within an acceptable range, followed by chip binning based on parameter sensitivities to extend TSOA.
The key findings are as follows. (1) The β increases with low junction temperature limits and high input voltages. However, this effect weakens as thermal constraints are relaxed, showing negligible voltage dependence. (2) The influence of parameter variability on TSOA is frequency dependent. At 10 kHz switching frequencies, TSOA remains nearly unchanged from the baseline, with β increasing by only 0.6% and stabilizing at 1.89% as variation expands. In contrast, at 50 kHz switching frequencies, TSOA contracts significantly, with β rising to 6.84% when the variation range reaches 3σ. (3) Parameter sensitivity shifts with frequency. The mean value of on-state resistance (Rds(on)) and transconductance (gfs) dominate at low frequencies. In contrast, the ranges of threshold voltage (Vth) and gate-source voltage (Vgs@Id_rating) become critical at high switching frequencies, where the current reaches the rated value in the transfer characteristics. (4) To extend TSOA, a two-step approach is proposed. First, Monte Carlo simulations determine the parameter variation threshold to maintain the overall TSOA reduction rate within an acceptable range, thereby guiding the selection of chips. Next, multi-objective optimization forms parallel chip groups, thereby extending the TSOA of multi-chip parallel power modules.
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Received: 30 January 2025
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2025, Vol. 40 
