Abstract：The fatigue failure of silicon carbide-based metal-oxide-semiconductor field-effect transistor（SiC MOSFET）caused by strong electro-thermal stresses poses a significant challenge to the reliability of traction converters. However, the effects of different gate structures（e.g., planar-gate and trench-gate）are rarely considered in many methods, which may lead to inaccurate predictions of remaining useful lifetime. This paper analyzes the failure mechanisms and the remaining useful lifetime prediction of SiC MOSFETs with different gate structures using power cycling tests（PCTs). The impact of process variations in gate structure on junction temperature（Tj）calibration is investigated. Using the temperature-sensitive electrical parameter（TSEP）calibration method and computer-aided design（TCAD）simulations, it is shown that trench-gate SiC MOSFETs exhibit notable process variations that degrade calibration accuracy at low gate-off voltages. Simulation results indicate that an insufficient negative gate voltage fails to fully close the channel, causing part of the measurement current to flow through the channel rather than through the body diode. Therefore, a sufficient negative gate voltage（Vgs=-10 V）is determined to ensure the channel is fully closed, thereby guaranteeing the accuracy of Tj monitoring during PCTs. Then, the degradation characteristics of the static and dynamic parameters are analyzed using the PCTs. For the saturation voltage drop Vds, a planar-gate SiC MOSFET exhibits a typical three-stage aging trajectory: slow decline, stepped increase, and oscillation. In contrast, trench-gate SiC MOSFETs skip the stepped increase stage, directly entering oscillation and vertical rise. Such behavior stems from the vertical current path in trench structures. Failure of a single bond wire causes a sharp increase in current density and thermal stress in the remaining wires, triggering a cascade failure. Regarding the threshold voltage Vth, planar-gate SiC MOSFETs show a continuous negative drift, primarily dominated by interface-state charge Qit. However, trench-gate SiC MOSFETs show an initial negative shift followed by a positive reversal due to the high electric field at the trench corners, which promotes the generation of gate-oxide trap Qot and acceptor-type interface states that eventually outweigh the initial negative drift. In dynamic parameters, planar and trench-gate SiC MOSFETs show opposing trends. The turn-on delay time td.on and rise time tr decrease for planar-gate SiC MOSFET due to negative Vth drift, but increase for trench gate SiC MOSFET from positive Vth offset. Additionally, both structures exhibit increased switching losses（Eon,Eoff）as package degradation raises the on-state resistance. Furthermore, the mechanisms of competitive failure are elucidated using finite element analysis（FEA). In a planar-gate SiC MOSFET, the uniform electric-field distribution suppresses gate-oxide degradation, making bond-wire fatigue the dominant failure mode. Trench-gate SiC MOSFET exhibits a synergistic degradation mechanism. As a result, chip degradation actively promotes package failure. Finally, the remaining useful lifetime of the two gate structures is compared using Weibull distribution fitting based on PCTs. The results suggest that the trench-gate SiC MOSFET exhibits a longer fatigue life than that of the planar-gate SiC MOSFET. The main reason is that the vertical trench structure facilitates heat conduction through the substrate, effectively reducing the junction temperature in the channel region. In contrast, the planar structure tends to accumulate heat near the surface.
敬德宝, 王惠民, 许智亮, 赵金山, 葛兴来. 基于功率循环实验的不同栅极结构SiC MOSFET失效机理对比分析[J]. 电工技术学报, 2026, 41(16): 5505-5520.
Jing Debao, Wang Huimin, Xu Zhiliang, Zhao Jinshan, Ge Xinglai. Failure Mechanism Analysis of SiC MOSFET with Different Gate Structures Based on Power Cycling Tests. Transactions of China Electrotechnical Society, 2026, 41(16): 5505-5520.
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