Behavior Model of High-Voltage SiC MOSFET’s Short-Circuit Fault Based on Device Physics
Wu Yifan1, Li Chi1, Xu Yunfei2, Zheng Zedong1, Hao Yi2
1. State Key Laboratory of Power System Operation and Control Tsinghua University Beijing 100084 China; 2. State Grid Smart Grid Research Institute Co. Ltd Beijing 102209 China
Abstract：The short-circuit ruggedness of silicon carbide (SiC) MOSFETs represents a significant challenge that impedes their widespread adoption in high-voltage applications. Developing effective short-circuit protection strategies in domestic high-voltage SiC MOSFETs is hampered by a lack of robust technical expertise and empirical experience. Furthermore, the absence of fast and accurate simulation models presents a fundamental obstacle to advancing research on the application of domestic high-voltage SiC MOSFETs. Traditional behavioral models focus on fitting these devices’ static and dynamic characteristics but fail to simulate fault conditions adequately. Recently, several models have been proposed for short-circuit scenarios. However, these models exhibit limitations, including low adaptability for high-voltage devices, insufficient universality, and inefficient parameter extraction. This paper introduces a behavioral model for high-voltage SiC MOSFETs, which incorporates practical physical characteristics. The proposed model can accurately simulate the device's behavior-such as voltage and current dynamics-throughout a short-circuit fault event. The behavioral model comprises five primary components: a controlled current source (ICH) for calculating the current flowing through the channel, a controlled current source (ILEAK) for assessing the leakage current under high junction temperature conditions, a diode (D) representing the device's body diode, capacitors (CGS, CGD and CDS) for the junction capacitances, and a resistor (RD) denoting the total resistance of the drift layer and JFET region of the device. In high-voltage devices, the resistances associated with the drift layer and JFET region constitute a significantly large proportion of the total on-resistance compared to devices rated below 1.2 kV. The increased resistance markedly influences the device's behavior during short-circuit faults. Consequently, RD is carefully calculated based on the practical structure of high-voltage SiC MOSFETs and the current path during short-circuit events at the cell level. The model’s parameters are categorized into four types, each with detailed extraction methods. Furthermore, key physical parameters that are challenging to measure-such as intrinsic carrier concentration (ni), threshold voltage (VT), and carrier mobility (μ)-are calculated based on semiconductor physics principles. The strong physical significance of the model's components and the parameters enhances the universality and portability of the proposed model. A 6.5 kV/400 A SiC MOSFET produced by the State Grid Smart Grid Research Institute Co. Ltd is modeled. The model is developed, and short-circuit test simulations are conducted using Matlab/Simulink. A short-circuit test experimental platform is established for the selected device. Short-circuit tests are performed under a short-circuit duration (tSC) of 2.5 μs and DC-bus voltages (VDC) of 3 300 V and 2 470 V. The high consistency between the simulated and experimental waveforms indicates that the presented model effectively simulates the behavior of high-voltage SiC MOSFETs during short-circuit faults. The relative errors of the current rise rate and peak short-circuit current are less than 2.20% and 0.83%. Additionally, the relative errors of simulated peak currents with the low-voltage models are 7.58% and 5.89% under VDC=3 300 V and VDC=2 470 V, respectively, seven times those with the proposed model.
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