应用于级联STATCOM的高精度低成本全FPGA实时仿真模型研究

doi:10.19595/j.cnki.1000-6753.tces.171622

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Abstract A fully field-programmable-gate-arrays (FPGA) based real-time simulation with high fidelity and low cost for the cascaded static synchronous compensator (STATCOM) is proposed in this paper. To improve the fidelity of the simulation with small time-step, a modified switching-function model is adopted to separate the active switches from the circuit network for computation effort reduction. With the help of external circuit voltage calculation and comparison logic, dead-time period can be covered to improve the precision of model simulation. The real-time detection of the H-bridge state ensures the unidirectional conductivity of diode to achieve the simulation accuracy. To take the hardware resource consumption and simulation step into account, serial and parallel combination design as well as deep pipelining technology is employed for the model implementation. The STATCOM of 12 cascaded H-bridges was implemented on a single FPGA chip of Cyclone IV EP4CE115, and the simulation step can reach 0.85μs. The results of the Simulink/PSIM simulation and real system prototype experiment demonstrate the effectiveness of the proposed real-time simulation.

Key words： Real-time simulation cascaded STATCOM field-programmable-gate-arrays (FPGA) modified switching-function model

Received: 29 November 2017 Published: 01 March 2019

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TM46

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	Articles by authors
	Zhu Jianxin
	Hu Haibing
	Lu Daorong
	Yao Jianhui
	Wang Sen
	Xing Yan

Cite this article:

Zhu Jianxin,Hu Haibing,Lu Daorong等. The Research on Fully FPGA-Based Real-Time Simulation with High Fidelity and Low Cost for the Cascaded STATCOM[J]. Transactions of China Electrotechnical Society, 2019, 34(4): 777-785.

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https://dgjsxb.ces-transaction.com/EN/10.19595/j.cnki.1000-6753.tces.171622 OR https://dgjsxb.ces-transaction.com/EN/Y2019/V34/I4/777

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