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| Analytical Characterization of Trapped Charge in SiC MOSFETs Using Subthreshold Swing Method and Its Application in Bias Temperature Instability Mechanism Analysis |
| Shi Chao1,2,3, Li Xuebao2,3,4, Wang Laili1, Wang Yue1, Jiang Xinyu2,3,4, Chen Zhongyuan2,3, Ran Li2,3,5 |
1. State Key Laboratory of Electrical Insulation and Power Equipment Xi’an Jiaotong University Xi’an 710049 China;
2. Beijing Huairou Laboratory Beijing 101499 China;
3. Beijing Institute of Smart Energy Beijing 102209 China;
4. State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources North China Electric Power University Beijing 102206 China;
5. State Key Laboratory of Power Transmission Equipment Technology Chongqing University Chongqing 400044 China |
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Abstract Owing to superior performance metrics in blocking voltage, operating temperature, switching speed, and switching loss, SiC MOSFETs are gradually replacing traditional silicon-based devices in fields such as photovoltaics and electric vehicles. Nevertheless, the widespread adoption of SiC MOSFETs is hindered by critical reliability challenges, particularly their exceptionally high interface state density (DIT), which induces threshold voltage drift under bias temperature instability (BTI) and severely compromises gate oxide reliability. Therefore, it is necessary to characterize the interface state density to analyze the degradation mechanism of devices under BTI.
Conventional DIT characterization methods predominantly rely on capacitance-voltage (C-V) measurements, which unavoidably face the challenge of decoupling the interface trap capacitance (CIT) from the total measured capacitance. Alternatively, some methods require specialized equipment, often involving complex protocols and time-consuming measurement cycles. In contrast, the method based on analyzing the slope change of the I-V characteristic in the subthreshold region is simple, rapid, and convenient, making it particularly suitable for characterizing degraded devices. In this work, the classical I-V method is further developed into an analytical expression of the subthreshold swing (SS) to DIT using the concept of infinitesimal analysis. On one hand, it circumvents the difficulty of precisely separating CIT, enabling measurements on conventional MOSFET devices without the need for special test structures. On the other hand, the proposed formula links DIT to SS, revealing an explicit linear proportionality between the two. Consequently, researchers can infer the distribution of DIT across the energy band by observing how the SS varies with energy level, which is crucial for understanding the impact of interface states and improving device performance.
Furthermore, to minimize the influence of factors other than initial voltage stress amplitude, stress time, and temperature, the paper discusses the roles of scan direction, scan speed, scan delay time, measurement time, and charge-clearing pretreatment. The results indicate that: (1) the device must be shorted to ground before every change of measurement condition to erase residual stress history; (2) I-V characteristics should be recorded with a descending step-voltage waveform rather than an ascending scan to prevent underestimation of trapped charge arising from surface-polarity reversal; and (3) reducing both scan delay and measurement time increases the effective scan rate, thus maximizing the retention of the effect of initial electrothermal stress on trapped charge.
Finally, the effects of different electrothermal stress conditions, including initial voltage stress amplitude, stress time, and temperature, are quantified. The results show that the variation of trapped charge correlates strongly with the magnitude of threshold voltage drift, demonstrating that trapped charge variation is the principal driver of this drift. Due to the charge-memory characteristic of traps, distinct electrothermal stress histories result in different amounts of charge captured in device traps, leading to non-uniform threshold voltage drift. The intrinsically high DIT of SiC MOSFETs produces a large SS at low temperature, which deteriorates further with increasing electrothermal stress. Under favorable electrothermal stress conditions, the initial voltage-stress amplitude scales approximately linearly with both trapped charge and threshold-voltage drift. In contrast, the initial voltage-stress time exhibits an exponential dependence on both of these quantities.
These findings provide rapid assessment guidance of DIT and offer efficient tools for accelerating the process production testing flow and enhancing the gate oxide reliability of SiC MOSFETs.
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Received: 06 December 2024
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[1] 柯俊吉, 赵志斌, 谢宗奎, 等. 考虑寄生参数影响的碳化硅MOSFET开关暂态分析模型[J]. 电工技术学报, 2018, 33(8): 1762-1774.
Ke Junji, Zhao Zhibin, Xie Zongkui, et al.Analytical switching transient model for silicon carbide MOSFET under the influence of parasitic parameters[J]. Transa- ctions of China Electrotechnical Society, 2018, 33(8): 1762-1774.
[2] 王来利, 赵成, 张彤宇, 等. 碳化硅功率模块封装技术综述[J]. 电工技术学报, 2023, 38(18): 4947-4962.
Wang Laili, Zhao Cheng, Zhang Tongyu, et al.Review of packaging technology for silicon carbide power modules[J]. Transactions of China Electro- technical Society, 2023, 38(18): 4947-4962.
[3] 江芙蓉, 杨树, 盛况. 碳化硅MOSFET特征参数随温度变化的比较研究[J]. 电源学报, 2018, 16(6): 143-151.
Jiang Furong, Yang Shu, Sheng Kuang.Comparative study on temperature-dependent characteristic parameters of SiC MOSFET[J]. Journal of Power Supply, 2018, 16(6): 143-151.
[4] 张少昆, 孙微, 范涛, 等. 基于分立器件并联的高功率密度碳化硅电机控制器研究[J]. 电工技术学报, 2023, 38(22): 5999-6014.
Zhang Shaokun, Sun Wei, Fan Tao, et al.Research on high power density silicon carbide motor controller based on parallel connection of discrete devices[J]. Transactions of China Electrotechnical Society, 2023, 38(22): 5999-6014.
[5] 李锦, 党恩帅, 范雨顺, 等. 一种碳化硅与硅器件混合型三电平有源中点钳位零电压转换软开关变流器[J]. 电工技术学报, 2024, 39(8): 2496-2510.
Li Jin, Dang Enshuai, Fan Yushun, et al.A hybrid three-level active-neutral-point-clamped zero-voltage transition soft-switching converter with silicon carbide and silicon devices[J]. Transactions of China Electrotechnical Society, 2024, 39(8): 2496-2510.
[6] 肖标, 郭祺, 涂春鸣, 等. 面向开关时序与驱动电压自主协同调控的SiC/Si混合开关驱动电路[J]. 电工技术学报, 2025, 40(4): 1117-1128.
Xiao Biao, Guo Qi, Tu Chunming, et al.SiC/Si hybrid switch drive circuit with autonomous and coordinated control of switching sequences and driving voltages[J]. Transactions of China Electrotechnical Society, 2025, 40(4): 1117-1128.
[7] Xie Minghang, Sun Pengju, Wang Kaihong, et al.Online gate-oxide degradation monitoring of planar SiC MOSFETs based on gate charge time[J]. IEEE Transactions on Power Electronics, 2022, 37(6): 7333-7343.
[8] Qi Jinwei, Yang Xu, Li Xin, et al.Temperature dependence of dynamic performance characterization of 1.2-kV SiC power MOSFETs compared with Si IGBTs for wide temperature applications[J]. IEEE Transactions on Power Electronics, 2018, 34(9): 9105-9117.
[9] Tanimoto Y, Saito A, Matsuura K, et al.Power-loss prediction of high-voltage SiC-mosfet circuits with compact model including carrier-trap influences[J]. IEEE Transactions on Power Electronics, 2016, 31(6): 4509-4516.
[10] Cai Yumeng, Chen Cong, Zhao Zhibin, et al.Characterization of gate-oxide degradation location for SiC MOSFETs based on the split C-V method under bias temperature instability conditions[J]. IEEE Transactions on Power Electronics, 2023, 38(5): 6081-6093.
[11] Terman L M.An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide- silicon diodes[J]. Solid-State Electronics, 1962, 5(5): 285-299.
[12] Nicollian E H, Goetzberger A.The Si-SiO, interface- electrical properties as determined by the metal- insulator-silicon conductance technique[J]. The Bell System Technical Journal, 1967, 46(6): 1055-1033.
[13] Yoshioka H, Nakamura T, Kimoto T.Generation of very fast states by nitridation of the SiO2/SiC interface[J]. Journal of Applied Physics, 2012, 112(2): 024520.
[14] Hauck M, Weisse J, Lehmeyer J, et al.Quantitative investigation of near interface traps in 4H-SiC MOSFETs via drain current deep level transient spectroscopy[C]//2016 European Conference on Silicon Carbide & Related Materials (ECSCRM), Halkidiki, Greece, 2016: 1.
[15] Salinaro A, Pobegen G, Aichinger T, et al.Charge pumping measurements on differently passivated lateral 4H-SiC MOSFETs[J]. IEEE Transactions on Electron Devices, 2015, 62(1): 155-163.
[16] (美)施敏, 伍国珏. 半导体器件物理[M]. 耿莉, 张瑞智, 译. 西安: 西安交通大学出版社, 2023.
[17] DasGupta S, Brock, Kaplar R, et al. Extraction of trapped charge in 4H-SiC metal oxide semiconductor field effect transistors from subthreshold characteri- stics[J]. Applied Physics Letters, 2011, 99(2): 023503.
[18] Hughart D R, Flicker J D, Atcitty S, et al. Sensitivity analysis of a technique for the extraction of interface trap density in SiC MOSFETs from subthreshold characteristics[C]//2014 IEEE International Reliabi- lity Physics Symposium, Waikoloa, HI, USA, 2014: 2C.2.1-2C.2.6.
[19] Schroder D K.Semiconductor material and device characterization[M]. New Jersey: John Wiley & Sons, 2005.
[20] Ortiz Gonzalez J A, Alatise O. A novel non-intrusive technique for BTI characterization in SiC MOSFETs[J]. IEEE Transactions on Power Electronics, 2018, 34(6): 5737-5747.
[21] Lelis A J, Habersat D, Lopez G, et al. Bias stress- induced threshold-voltage instability of SiC MOSFETs[J]. Materials Science Forum, 2006, 527-529: 1317-1320.
[22] Liang Ye, Zhang Yuanlei, Zhang Jingqun, et al.Characterization of oxide trapping in SiC MOSFETs under positive gate bias[J]. IEEE Journal of the Electron Devices Society, 2022, 10: 920-926.
[23] Guo Chunsheng, Cui Shaoxiong, Li Yumeng, et al.Study of the influence of different gate oxide traps on threshold voltage drift of SiC MOSFET based on transient current[J]. IEEE Transactions on Power Electronics, 2024, 39(8): 9629-9637.
[24] Karki U, González-SantiniN S, Peng F Z, et al. Effect of gate- oxide degradation on electrical parameters of silicon carbide MOSFETs[J]. IEEE Transactions on Electron Devices, 2020, 67(6): 2544-2552.
[25] LelisA J. Cause and effect of threshold-voltage instability on the reliability of silicon-carbide MOSFETs[D]. Maryland: University of Maryland, 2011.
[26] Kimoto T, Cooper J A.Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications[M]. Singapore: John Wiley & Sons Singapore Pte. Ltd., 2014.
[27] Baliga B.Jayant. Fundamentals of Power Semicon- ductor Devices[M]. Cham: Springer International Publishing AG, 2019.
[28] Lelis A J, Habersat D, Green R, et al.Time depen- dence of bias-stress-induced SiC MOSFET threshold- voltage instability measurements[J]. IEEE Transa- ctions on Electron Devices, 2008, 55(8): 1835-1840.
[29] Rescher G, Pobegen G, Aichinger T, et al.Precon- ditioned BTI on 4H-SiC: proposal for a nearly delay time-independent measurement technique[J]. IEEE Transactions on Electron Devices, 2018, 65(4): 1419-1426.
[30] Yang Chao, Wei Shengsheng, Wang Dejun.Bias temperature instability in SiC metal oxide semicon- ductor devices[J]. Journal of Physics D: Applied Physics, 2021, 54(12): 123002.
[31] Shintani M, Nakamura Y, Oishi K, et al.Surface- potential-based silicon carbide power MOSFET model for circuit simulation[J]. IEEE Transactions on Power Electronics, 2018, 33(12): 10774-10783.
[32] Albrecht M, Klupfel F J, Erlbacher T.An iterative surface potential algorithm including interface traps for compact modeling of SiC-MOSFETs[J]. IEEE Transactions on Electron Devices, 2020, 67(3): 855-862.
[33] Wei Jiaxin, Wei Zhaoxiang, Hao Fu, et al.Review on the reliability mechanisms of SiC Power MOSFETs: a comparison between planar-gate and trench-gate structures[J]. IEEE Transactions on Power Electronics, 2023, 38(7): 8990-9005.
[34] Wang Ying, Lin Mao, Li Xingji, et al.Single-event burnout hardness for the 4H-SiC trench-gate MOSFETs based on the multi-island buffer layer[J]. IEEE Transa- ctions on Electron Devices, 2019, 66(10): 4264-4272.
[35] Li Ping, Ma Rongyao, Shen Jingyu, et al.A novel SiC MOSFET with a fully depleted P-base MOS-channel diode for enhanced third quadrant performance[J]. IEEE Transactions on Electron Devices, 2022, 69(8): 4438-4443.
[36] Habersat D B, Lelis A J, Green R, et al.Comparison of test methods for proper characterization of VT in SiC MOSFETs[J]. Materials Science Forum, 2016, 858: 833-839.
[37] Vasilev A, Jech M, Grill A, et al.TCAD modeling of temperature activation of the hysteresis characteri- stics of lateral 4H-SiC MOSFETs[J]. IEEE Transa- ctions on Electron Devices, 2022, 69(6): 3290-3295. |
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2025, Vol. 40 
