Research on Multi-Objective Optimization Design of Double-Sided Cooling SiC Power Module Based on Intelligent Algorithm
Zhang Jin1, Liu Zhi1, Liu Yi1, Wang Jianpeng1, Liu Zhihong2, Yamazaki Tomoyuki3, Wang Laili1
1. State Key Laboratory of Electrical Insulation and Power Equipment(Xi'an Jiaotong University),Xi'an 710049 China;
2. Star Power Semiconductor Ltd., Jiaxing 314006, Zhejiang Province, China;
3. Fuji Electric Company Ltd,. Ishikawa 921-8001, Japan
Double-sided cooling power module has low parasitic parameters and excellent heat dissipation performance, which is one of the development directions of power modules. However, the electrical, thermal and mechanical properties of it are contradictory to each other, so it is difficult to achieve the full optimization of all performance. As a new type of packaging structure, double-sided cooling power module lacks systematic multi-objective optimization design method. Therefore, this paperproposes a multi-objective optimization design method based on intelligent algorithm.
Firstly, the structure of the double-sided cooling SiC power module was designed and the material of each key component within the module was determined. The electrical, thermal and mechanical properties of the designed power module were analyzed by parasitic parameter simulation and finite element electro-thermal coupling simulation, the electrical properties, i.e. parasitic inductance,were calculated using ANSYS Q3D. The thermal properties, i.e. junction-to-ambient thermal resistance,were calculated using COMSOL. The mechanical properties, including die attach stress and chip stress, were calculated using COMSOL considering the temperature gradient in the heat conduction process.After that, the influence of the size parameters on the performance indexes of the power module was studied,there are three key points, the point one is that h2 has a large effect on the parasitic inductance through Eddy current effect, the point two is that a negative relationship between h1 and the thermal resistance exists because a thicker copper layer can spread more heat horizontally, the point three is that the optimization direction of chip stress and the die attach stress is contradicted to each other.
Secondly, a multi-objective optimization method based on intelligent algorithm was proposed using the method of parametric modeling and simulation. Based on the randomly generated size parameters, hundreds of module samples underwentparametric simulation, then these results were used as training samples for artificial neural network.The functional relationship between size parameters and performance indexes can be obtained, which can speed up the calculation of performance index while ensuring the calculation accuracy. After the objective function is obtained, genetic algorithm is used to solve the multi-objective optimization. A three-objective optimization of die attach stress, parasitic inductance and thermal resistance was conducted, the Pareto front is a curve because thermal resistance and die attach stress have the same optimization direction. Then a three-objective optimization of chip stress, parasitic inductance and thermal resistance was conducted, and the Pareto front is a curved surface, because these three performances index have different optimization direction.To achieve customized optimization, a stricter size constraint was set and a four-objective optimization of die attach stress, chip stress, parasitic inductance and junction-to-ambient thermal resistance was conducted and a solution that can improve all performance exists.
Finally, based onfour-objective optimization,the initial power module before optimization and the power module after optimization weremanufactured respectively, and their performance indexeswere tested and compared, the parasitic inductance was measured using LCR meter, junction-to-ambient thermal resistance was measured using a thermal characteristic test platform. The results showthat the multi-objective optimization method can significantly improve overall performance ofthe double-sided cooling SiC power module, the loop parasitic inductance is reduced from 7.475nH to 6.489nH, the thermal resistance is reduced from 0.373K/W to 0.355K/W.
张缙, 刘智, 刘意, 王见鹏, 刘志红, 山崎智幸, 王来利. 基于智能算法的双面散热SiC功率模块多目标优化设计[J]. 电工技术学报, 0, (): 230621-230621.
Zhang Jin, Liu Zhi, Liu Yi, Wang Jianpeng, Liu Zhihong, Yamazaki Tomoyuki, Wang Laili. Research on Multi-Objective Optimization Design of Double-Sided Cooling SiC Power Module Based on Intelligent Algorithm. Transactions of China Electrotechnical Society, 0, (): 230621-230621.
[1] 王来利,赵成,张彤宇,闫飞飞.碳化硅功率模块封装技术综述[J/OL].电工技术学报:1-16[2022-09-23].DOI:10.19595/j.cnki.1000-6753.tces.221214. Wang Laili, Zhao Cheng, Zhang Tongyu, et al. Review of Packaging and Integration Technology inSilicon Carbide Power modules[J/OL]. Transactions of China ElectrotechnicalSociety, 1-16[2022-09-23], DOI10.19595/j.cnki.1000-6753.tces.221214.
[2] Temple V, Waldron J, Azotea J, et al.High frequency SiC majority carrier modules[C]//Proceedings of PCIM Europe 2015; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany, 2015: 1-7.
[3] Kasko I, Berberich S E, Gross M, et al.High efficient approach to utilize SiC MOSFET potential in power modules[C]//2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), Sapporo, Japan, 2017: 259-262.
[4] Yang Fengtao, Jia Lixin, Wang Laili, et al.Interleaved planar packaging method of multichip SiC power module for thermal and electrical performance improvement[J]. IEEE Transactions on Power Electronics, 2022, 37(2): 1615-1629.
[5] Vagnon E, Jeannin P O, Crebier J C, et al.A bus-bar-like power module based on three-dimensional power-chip-on-chip hybrid integration[J]. IEEE Transactions on Industry Applications, 2010, 46(5): 2046-2055.
[6] Liang Zhenxian, Ning Puqi, Wang F.Development of advanced all-SiC power modules[J]. IEEE Transactions on Power Electronics, 2014, 29(5): 2289-2295.
[7] Mu Wei, Wang Laili, Wang Binyu, et al.Direct integration of optimized phase-change heat spreaders into SiC power module for thermal performance improvements under high heat flux[J]. IEEE Transactions on Power Electronics, 2022, 37(5): 5398-5410.
[8] Ni Ze, Lyu Xiaofeng, Yadav O P, et al.Overview of real-time lifetime prediction and extension for SiC power converters[J]. IEEE Transactions on Power Electronics, 2020, 35(8): 7765-7794.
[9] Dornic N, Khatir Z, Tran S H, et al.Stress-based model for lifetime estimation of bond wire contacts using power cycling tests and finite-element modeling[J]. IEEE Journal of Emerging and Selected Topics in Power Electronics, 2019, 7(3): 1659-1667.
[10] Lee H, Smet V, Tummala R.A review of SiC power module packaging technologies: challenges, advances, and emerging issues[J]. IEEE Journal of Emerging and Selected Topics in Power Electronics, 2020, 8(1): 239-255.
[11] Ding Chao, Liu H, Ngo K D T, et al. A double-side cooled SiC MOSFET power module with sintered-silver interposers: I-design, simulation, fabrication, and performance characterization[J]. IEEE Transactions on Power Electronics, 2021, 36(10): 11672-11680.
[12] 曾正, 李晓玲, 林超彪, 等. 功率模块封装的电-热-力多目标优化设计[J]. 中国电机工程学报, 2019, 39(17): 5161-5171, 5297.
Zeng Zheng, Li Xiaoling, Lin Chaobiao, et al.Electric-thermal-stress oriented multi-objective optimal design of power module package[J]. Proceedings of the CSEE, 2019, 39(17): 5161-5171, 5297.
[13] 曾正, 欧开鸿, 吴义伯, 等. 车用双面散热功率模块的热-力协同设计[J]. 电工技术学报, 2020, 35(14): 3050-3064.
Zeng Zheng, Ou Kaihong, Wu Yibo, et al.Thermo-mechanical Co-design of double sided cooling power module for electric vehicle application[J]. Transactions of China Electrotechnical Society, 2020, 35(14): 3050-3064.
[14] Ji Bing, Song Xueguan, Sciberras E, et al.Multiobjective design optimization of IGBT power modules considering power cycling and thermal cycling[J]. IEEE Transactions on Power Electronics, 2014, 30(5): 2493-2504.
[15] 能立强. 多芯片并联SiC MOSFET模块的电-热-力多物理场仿真设计研究[D]. 天津: 天津大学, 2020.
[16] Hall S H, Hall G W, McCall J A. High-speed digital system design: a handbook of interconnect theory and design practices[M]. New York: Wiley, 2000
[17] Le Quang, Al Razi I, Evans T M, et al. Fast and accurate parasitic extraction in multichip power module design automation considering eddy-current losses[J]. IEEE Journal of Emerging and Selected Topics in Power Electronics, 2022, PP(99): 1.
[18] Wang Jianpeng, Chen Wenjie, Wang Laili, et al.A transient 3-D thermal modeling method for IGBT modules considering uneven power losses and cooling conditions[J]. IEEE Journal of Emerging and Selected Topics in Power Electronics, 2021, 9(4): 3959-3970.
[19] 陈宇, 周宇, 罗皓泽, 等. 计及芯片导通压降温变效应的功率模块三维温度场解析建模方法[J]. 电工技术学报, 2021, 36(12): 2459-2470.
Chen Yu, Zhou Yu, Luo Haoze, et al.Analytical 3D temperature field model for power module considering temperature effect of semiconductor voltage drop[J]. Transactions of China Electrotechnical Society, 2021, 36(12): 2459-2470.
[20] Le Henaff F, Azzopardi S, Woirgard E, et al.Lifetime evaluation of nanoscale silver sintered power modules for automotive application based on experiments and finite-element modeling[J]. IEEE Transactions on Device and Materials Reliability, 2015, 15(3): 326-334.
[21] Dragičević T, Wheeler P, Blaabjerg F.Artificial intelligence aided automated design for reliability of power electronic systems[J]. IEEE Transactions on Power Electronics, 2018, 34(8): 7161-7171.
[22] Wang Jianpeng, Chen Wenjie, Wu Yuwei, et al.Chip-level electrothermal stress calculation method of high-power IGBT modules in system-level simulation[J]. IEEE Transactions on Power Electronics, 2022, 37(9): 10546-10561.
[23] (美)埃德温,(美)扎克著;孙志强等译.最优化导论[M].北京:电子工业出版社,2015.
[24] 袁立强, 陆子贤, 孙建宁, 等. 电能路由器设计自动化综述—设计流程架构和遗传算法[J]. 电工技术学报, 2020, 35(18): 3878-3893.
Yuan Liqiang, Lu Zixian, Sun Jianning, et al.Design automation for electrical energy router-design workflow framework and genetic algorithm: a review[J]. Transactions of China Electrotechnical Society, 2020, 35(18): 3878-3893.
[25] 陈杰, 邓二平, 赵子轩, 等. 不同老化试验方法下SiC MOSFET失效机理分析[J]. 电工技术学报, 2020, 35(24): 5105-5114.
Chen Jie, Deng Erping, Zhao Zixuan, et al.Failure mechanism analysis of SiC MOSFET under different aging test methods[J]. Transactions of China Electrotechnical Society, 2020, 35(24): 5105-5114.