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| The Current Balance Analysis and Optimization Design of the Laminated Busbar with Discrete Devices in Parallel |
| Yu Shaolin1, Zhang Xing1, Wang Jianing1,2, Zhou Weinan1, Huang Yaodong1 |
1. National and local Joint Engineering Laboratory for Renewable Energy Access to Grid Technology Hefei University of Technology Hefei 230009 China;
2. Institute of Energy Hefei Comprehensive National Science Center Hefei 230088 China |
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Abstract To accommodate high-power power conversion application scenarios, the SiC MOSFETs must be used in parallel. In medium and high-power inverters, the laminated busbar with low parasitic inductance characteristics is usually used as an interconnection structure for DC-link capacitors and power devices. An asymmetrical laminated busbar structure can lead to asymmetrical parasitic parameters, which in turn causes unbalanced current distribution among the parallel devices. Therefore, in addition to the low parasitic inductance, the symmetry of the parasitic parameter for each parallel branch is a critical design factor for the laminated busbar with discrete devices in parallel. This paper analyzed the current sharing performance of the laminated busbar with six discrete devices in parallel and further optimized the busbar structure.
Firstly, the equivalent parasitic parameters of each parallel branch of the original laminated busbar are extracted by the established parasitic parameter model. The results show that the equivalent parasitic inductance and parasitic resistance of each parallel branch are unbalanced in the static process. The effect of the unbalanced parasitic parameters on the current distribution among the paralleled devices is analyzed by the established double-pulse simulation circuit. It is shown that reducing the switching speed can weaken the effect of the parasitic inductance variability on the dynamic current imbalance. In the context of large-load applications, it is necessary to pay more attention to the effect of parasitic resistance differences on the static current imbalance.
Then, aiming at the extraction accuracy of the static parasitic parameters for the laminated busbar with discrete devices in parallel, this paper proposes a sink location method. It points out that the current sink should be the maximum point of the aggregated current, while the impedance after the point does not affect the current distribution. Based on this principle, the real sink point in the AC busbar is located in combination with the finite simulation software, which improves the extraction accuracy of static parasitic parameters. In addition, the mutual coupling effect on the parasitic parameters of the laminated busbar is explored. It is found that the presence of coupled mutual inductance will make it possible for the equivalent parasitic parameters of asymmetric parallel branches to be consistent. The original laminated busbar with six discrete devices in parallel is then optimized. By adjusting the position of the current sink point, thus matching the self-inductance and mutual inductance, the parasitic parameters of the parallel branch can be equalized. The parasitic parameters of the optimized laminated bus are extracted, and the results show that the parasitic parameters of each parallel branch are more balanced in the static process.
Finally, a double-pulse test platform was built to test the static currents of each parallel device of the optimized laminated busbar. Compared with the original laminated busbar, the experimental results show that the static unbalanced current has been greatly improved.
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Received: 19 May 2022
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[1] 邵伟华, 冉立, 曾正, 等. 基于优化对称布局的多芯片SiC模块动态均流[J]. 中国电机工程学报, 2018, 38(6): 1826-1836, 1920.
Shao Weihua, Ran Li, Zeng Zheng, et al.Dynamic current sharing of multichip SiC module with optimal symmetric layout[J]. Proceedings of the CSEE, 2018, 38(6): 1826-1836, 1920.
[2] Li Helong, Munk-Nielsen S, Bczkowski S, et al.A novel DBC layout for current imbalance mitigation in SiC MOSFET multichip power modules[J]. IEEE Transactions on Power Electronics, 2016, 31(12): 8042-8045.
[3] Zeng Zheng, Zhang Xin, Li Xiaoling.Layout- dominated dynamic current imbalance in multichip power module: mechanism modeling and comparative evaluation[J]. IEEE Transactions on Power Elec- tronics, 2019, 34(11): 11199-11214.
[4] 惠城武. SiC MOSFET并联模块均流技术研究[D]. 西安: 西安理工大学, 2018.
[5] Fabre J, Ladoux P.Parallel connection of 1200-V/ 100-A SiC MOSFET half-bridge modules[J]. IEEE Transactions on Industry Applications, 2016, 52(2): 1669-1676.
[6] Rabkowski J, Peftitsis D, Nee H P.Parallel-operation of discrete SiC BJTs in a 6-kW/250-kHz DC/DC boost converter[J]. IEEE Transactions on Power Electronics, 2014, 29(5): 2482-2491.
[7] 钟华, 刘志强, 宋佳茵, 等. 分立器件电机控制器功率单元设计与实现[J]. 汽车文摘, 2021(1): 42-47.
Zhong Hua, Liu Zhiqiang, Song Jiayin, et al.Design and implementation of intelligent power unit for discrete device motor controller[J]. Automotive Digest, 2021(1): 42-47.
[8] Chen C, Su Ming, Xu Zhuxian, et al.SiC-based automotive traction drives, opportunities and challen- ges[C]//IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Albuquerque, NM, 2017: 25-30.
[9] Yu Shaolin, Wang Jianing, Zhang Xing, et al.The potential impact of using traction inverters with SiC MOSFETs for electric buses[J]. IEEE Access, 2021, 9: 51561-51572.
[10] Hu Ji, Alatise O, Ortiz Gonzalez J A, et al. Robu- stness and balancing of parallel-connected power devices: SiC versus CoolMOS[J]. IEEE Transactions on Industrial Electronics, 2016, 63(4): 2092-2102.
[11] 曾正, 邵伟华, 胡博容, 等. 基于耦合电感的SiC MOSFET并联主动均流[J]. 中国电机工程学报, 2017, 37(7): 2068-2081.
Zeng Zheng, Shao Weihua, Hu Borong, et al.Active current sharing of paralleled SiC MOSFETs by coupling inductors[J]. Proceedings of the CSEE, 2017, 37(7): 2068-2081.
[12] Ke Junji, Zhao Zhibin, Sun Peng, et al.New screening method for improving transient current sharing of paralleled SiC MOSFETs[C]//International Power Electronics Conference, Niigata, Japan, 2018: 1125-1130.
[13] Tiwari S, Rabiei A, Shrestha P, et al.Design considerations and laboratory testing of power circuits for parallel operation of silicon carbide MOSFETs[C]//European Conference on Power Electronics and Applications, Geneva, Switzerland, 2015: 1-10.
[14] Qin Haihong, Zhang Ying, Zhu Ziyue, et al.Influences of circuit mismatch on paralleling silicon carbide MOSFETs[C]//IEEE Conference on Industrial Electronics and Applications, Siem Reap, Cambodia, 2018: 556-561.
[15] 黄华震, 柯俊吉, 孙鹏, 等. 寄生电感不匹配对SiC MOSFET并联电流分配的影响[J]. 半导体技术, 2018, 43(11): 833-840.
Huang Huazhen, Ke Junji, Sun Peng, et al.Influence of parasitic inductance mismatch on the parallel SiC MOSFETs current distribution[J]. Semiconductor Technology, 2018, 43(11): 833-840.
[16] 成林, 欧宏, 毕闯, 等. 基于SiC MOSFET的同步Buck变换器电磁干扰噪声分析及预测[J]. 电工技术学报, 2021, 36(增刊2): 627-634, 643.
Cheng Lin, Ou Hong, Bi Chuang, et al.Analysis and prediction of electromagnetic interference noise in synchronous Buck converter with SiC MOSFET[J]. Transactions of China Electrotechnical Society, 2021, 36(S2): 627-634, 643.
[17] 段卓琳, 张栋, 范涛. SiC电机驱动系统传导电磁干扰建模及预测[J]. 电工技术学报, 2020, 35(22): 4726-4738.
Duan Zhuolin, Zhang Dong, Fan Tao.Modeling and prediction of electromagnetic interference in SiC motor drive systems[J]. Transactions of China Electrotechnical Society, 2020, 35(22): 4726-4738.
[18] 刘妍, 杨晓峰, 闫成章, 等. 考虑寄生电感的谐振开关电容变换器电压尖峰抑制[J]. 电工技术学报, 2021, 36(12): 2627-2639.
Liu Yan, Yang Xiaofeng, Yan Chengzhang, et al.Suppression of voltage spike in resonant switched capacitor converter considering parasitic indu- ctance[J]. Transactions of China Electrotechnical Society, 2021, 36(12): 2627-2639.
[19] 刘博, 刘伟志, 董侃, 等. 基于全碳化硅功率组件的变流器母排杂散电感解析计算方法[J]. 电工技术学报, 2021, 36(10): 2105-2114.
Liu Bo, Liu Weizhi, Dong Kan, et al.Analytical calculation method for stray inductance of converter busbar based on full silicon carbide power module[J]. Transactions of China Electrotechnical Society, 2021, 36(10): 2105-2114.
[20] 金祝锋, 李威辰, 胡斯登, 等. 大容量电力电子装置中母排杂散电感提取方法的优化研究[J]. 电工技术学报, 2017, 32(14): 1-7.
Jin Zhufeng, Li Weichen, Hu Sideng, et al.Opti- mization inductance extraction of bus bar in large- capacity power electronic equipment[J]. Transactions of China Electrotechnical Society, 2017, 32(14): 1-7.
[21] Mehrabadi N R, Cvetkovic I, Wang Jun, et al.Busbar design for SiC-based H-bridge PEBB using 1.7kV, 400 a SiC MOSFETs operating at 100kHz[C]//IEEE Energy Conversion Congress and Exposition, Milwaukee, WI, USA, 2017: 1-7.
[22] 董玉斐, 罗皓泽, 杨贺雅, 等. 1.2MV·A混合钳位五电平变流模块的结构布局优化和叠层母排设计[J]. 电工技术学报, 2016, 31(8): 11-18.
Dong Yufei, Luo Haoze, Yang Heya, et al.Engineering design for structure and bus bar of 1.2MV·A hybrid clamped five-level converter module[J]. Transactions of China Electrotechnical Society, 2016, 31(8): 11-18.
[23] 朱俊杰, 原景鑫, 聂子玲, 等. 基于全碳化硅功率组件的叠层母排优化设计研究[J]. 中国电机工程学报, 2019, 39(21): 6383-6394.
Zhu Junjie, Yuan Jingxin, Nie Ziling, et al.Optimum design of planer busbar based on all-silicon carbide power module[J]. Proceedings of the CSEE, 2019, 39(21): 6383-6394.
[24] 阮杰, 刘畅, 李广卓, 等. 适用于器件并联型ANPC拓扑的低感叠层母排设计方法[J]. 高电压技术, 2019, 45(7): 2093-2100.
Ruan Jie, Liu Chang, Li Guangzhuo, et al.Design method of low-inductance laminated busbar for device-parallel ANPC circuit[J]. High Voltage Engin- eering, 2019, 45(7): 2093-2100.
[25] Chen Cai, Pei Xuejun, Chen Yu, et al.Investigation, evaluation, and optimization of stray inductance in laminated busbar[J]. IEEE Transactions on Power Electronics, 2014, 29(7): 3679-3693.
[26] 顾妙松, 崔翔, 彭程, 等. 外部汇流母排对压接型IGBT器件内部多芯片并联均流特性的影响[J]. 中国电机工程学报, 2020, 40(1): 234-245, 390.
Gu Miaosong, Cui Xiang, Peng Cheng, et al.Influence of the external busbar on current sharing performance inside a multi-chip press-pack IGBT device[J]. Proceedings of the CSEE, 2020, 40(1): 234-245, 390.
[27] 薛燕鹏, 刘钧, 苏伟, 等. 一种IGBT并联模块用交流母排的设计方法[J]. 电力电子技术, 2019, 53(2): 16-18.
Xue Yanpeng, Liu Jun, Su Wei, et al.A design method of AC busbar for paralleled-IGBT module[J]. Power Electronics, 2019, 53(2): 16-18.
[28] 王磊, 罗毅飞, 马天兆, 等. 功率回路杂散电感对IGBT并联均流的影响[J]. 电力电子技术, 2020, 54(4): 33-35.
Wang Lei, Luo Yifei, Ma Tianzhao, et al.Effect of stray inductance in power circuit on parallel current sharing of high-power IGBT modules[J]. Power Electronics, 2020, 54(4): 33-35.
[29] 房雷, 刘钧, 苏伟. 母排互感对IGBT模块并联动态均流的影响[J]. 电力电子技术, 2017, 51(10): 60-62.
Fang Lei, Liu Jun, Su Wei.The influence of busbar mutual inductance on current balancing of parallel IGBT[J]. Power Electronics, 2017, 51(10): 60-62.
[30] Zhang Ning, Wang Shuo, Zhao Hui.Develop parasitic inductance model for the planar busbar of an IGBT H bridge in a power inverter[J]. IEEE Transactions on Power Electronics, 2015, 30(12): 6924-6933.
[31] Wang Jianing, Yu Shaolin, Zhang Xing, et al.Accurate modeling of the effective parasitic para- meters for the laminated busbar connected with paralleled SiC MOSFETs[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(5): 2107-2120.
[32] Zhang Boyi, Wang Shuo.Parasitic inductance modeling and reduction for wire-bonded half-bridge SiC multichip power modules[J]. IEEE Transactions on Power Electronics, 2021, 36(5): 5892-5903. |
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2023, Vol. 38 
