Abstract：The dynamic performance of three-phase digital phase-locked loop (PLL) based on synchronous reference frame depends on the proportional and integral (PI) parameters, compensation errors of angular frequency and phase angle static bias. The nonlinear model of the PLL is proved to be globally asymptotically stable with the design of Lyapunov function, which assures the validity of the PI parameters designed on the linear model. A grid phase sequence identification method based on zero-crossing detection is presented to guarantee the correct compensation of the angular frequency static bias. And the hysteresis voltage for zero-crossing detection is deduced to obtain the largest anti-interference margin. The initial phase angle is identified during phase sequence identification, and it could be used to compensate the phase angle static bias. Then the set-up time of the PLL could be greatly shortened to the waiting time of the zero-crossing and the set-up time of zero-crossing error due to the hysteresis voltage. Finally, the advantages mentioned above are verified by simulations and experiments.
洪小圆, 吕征宇. 基于同步参考坐标系的三相数字锁相环[J]. 电工技术学报, 2012, 27(11): 203-210.
Hong Xiaoyuan, Lü Zhengyu. Three-Phase Digital Phase-Locked Loop Based on Synchronous Reference Frame. Transactions of China Electrotechnical Society, 2012, 27(11): 203-210.
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