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A Simplified Space Vector Pulse Width Modulation Method Based on ghγ Coordinates System for the Three-Level Four-Leg Inverter |
Zhang Zhi1,2, Chen Haohui1,2, Chen Sizhe2, Zhang Zhaoyun1, Li Yiyun1 |
1. School of Electrical Engineering and Intelligence Dongguan University of Technology Dongguan 523808 China; 2. School of Automation Guangdong University of Technology Guangzhou 510006 China |
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Abstract The topology of the three-level, four-leg neutral-point-clamped (3L4L-NPC) inverter is more complex than the traditional two-level and three-leg ones, which complicates the vector space (VS) and space vector pulse width modulation (SVPMW) algorithm. Traditional methods designate a subspace under the αβγ and abc coordinates system to simplify the VS. However, the disadvantages of excess tetrahedrons in the subspace, manually finding for redundant vectors, lots of storage space for switching sequences and poor scalability remain unsolved. This paper proposes a simplified SVPWM method based on the ghγ coordinates system. By decomposing the three-level VS into several two-level ones and designating the first small sectors as subspaces, combining the exact charge adjusting method for capacitance voltage on DC-side, duty cycles and switching sequences of the 3L4L-NPC inverter can be automatically calculated. Firstly, the decomposability of the three-level VS is discussed. Since it has the same characteristics in both horizontal and vertical dimensions as the two-level one, the three-level VS can be replaced by the two-level ones with redundant vectors as center points. Secondly, the two-level SVPWM method is simplified. Duty cycles and switching sequences can be calculated automatically through integer computation and space vector construction in the first small sector, which can be extended to the decomposed two-level VSs. Thirdly, rules for dividing the three-level VS are established. The selected two-level VS and its redundant vectors are calculated using the hexagonal layer where the reference voltage vector locates on gh plane and γ axis. Combining the improved two-level SVPWM method, tetrahedrons containing modulation information can be found without global searching. Finally, the charge that causes fluctuations in the capacitance voltage on the DC side is classified into three types: the charge difference left over from the previous modulation cycle, the initial supplementary charge in this cycle, and the adjustment charge provided by small vectors in this cycle. Charge error is caused by the first two types. The stability of capacitor voltages can be maintained by a linear calculation that makes the sum of the third type and the charge error zero. In addition, the above three-level modulation process is extended to make it applicable to multi-level inverters. Simulation of the algorithm was first performed on Matlab/Simulink platform. When the three-phase balanced reference voltage was set at different modulation ratios, the output voltage was three and five levels at smaller and larger modulation ratios, respectively, and the latter was closer to a sinusoidal waveform. Then, harmonics were injected into the reference voltage, which generated non-saddle modulation waves. The output voltages transformed their levels when the reference values crossed half of the DC source. Next, the voltages of two capacitors on the DC side were set at 250 V and 450 V with the modulation ratio of m=0.9 and DC source voltage at Vdc=700 V. After 0.025 s, the neutral-point potential reached relative equilibrium and was accompanied by three times oscillation of fundamental frequency with an amplitude of 0.63 V. Meanwhile, the neutral-point potential oscillations were less than 1 V when modulation ratios were less than or equal to 1. Furthermore, semi-physical simulations were carried out with dSPACE-SCALEXIO. The results showed that the three-level four-leg inverter could accurately output voltages with different modulation ratios and asymmetric voltages. A compared test was carried out when DC-side capacitor voltages were set at 100 V and 300 V. The conventional control method used about 30 ms to stabilize the voltage, and three times fluctuations occurred. In contrast, capacitor voltages could be balanced without 20 ms and maintained smoothly through the proposed method. In addition, a multi-level simulation with a large modulation ratio was implemented on a four-level four-leg inverter, which outputs three-phase line voltage with seven levels. The following conclusions can be drawn from the simulation and experimental analyses. (1) Compared with the traditional SVPMW method, the proposed one does not require manual decomposition of three-level VS and large storage space, and can automatically calculate duty cycles and switching sequences under different operating conditions. (2) The proposed neutral-point potential balancing method can make two capacitor voltages on the DC-side consistent more quickly by accurately calculating the capacitor charge. (3) The proposed modulation method can be extended to multi-level inverters by changing the level.
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Received: 06 June 2022
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