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| Multichip Integral Clip Bonding SiC Power Module Reverse Coupling Low Inductance Packaging Method |
| Zhang Tongyu1, Wang Laili1,2, Miao Yu1, Pei Yunqing1, Gan Yongmei1 |
1. State Key Laboratory of Electrical Insulation and Power Equipment Xi’an Jiaotong University Xi’an 710049 China;
2. Shaoxing Tongyue Semiconductor Institute Shaoxing 312099 China |
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Abstract The silicon carbide (SiC) power device has emerged as a promising candidate for replacing the silicon power device in power converters. SiC exhibits extremely high blocking voltage, high switching speed, and low loss. However, when SiC devices are utilized as power modules, their performance is constrained by the packaging. The conventional aluminum (Al) wire bonding, power terminals, laminated busbars, and even film capacitors introduce unacceptable parasitic inductance into the commutation loop of the SiC power module, thereby resulting in high voltage overshoots, oscillations, and increased switching losses. Therefore, this paper proposes a low-inductance packaging method for multichip SiC power modules.
Firstly, a theoretical derivation of the parasitic inductance is presented, encompassing both the self- inductance and mutual inductance. The available space restricts the optimization of the self-inductance within the power module, as the size and number of the dies cannot be decreased. Moreover, the SiC MOSFETs require an additional conduction path to route the gate signal out of the power module, which also enlarges the size. Consequently, it is challenging to reduce the parasitic inductance without altering the packaging method of the power module. The optimized packaging method should place more emphasis on the mutual-inductance cancellation effect.
In this paper, the upper surface interconnection of the SiC MOSFET is substituted from Al wire bonding to Cu clip bonding. Cu clip bonding has a large cross-sectional area, enabling it to handle higher currents. More significantly, the integral Cu clip forms an additional layer for the arrangement of the circuit layout inside the power module. This extra layer provided by the integral Cu clip is co-designed with the layout of the ceramic substrate. The directions of the current flow on the Cu clip and the ceramic substrate are arranged to be opposite. The mutual inductance resulting from the opposite currents on the Cu clip and the ceramic substrate significantly reduces the parasitic inductance within the SiC power module. In the simulation, the parasitic inductance within the power module is decreased to 3.8 nH.
The switching performance of the SiC MOSFET is influenced by the parasitic inductance of the commutation loop, which includes the inductance within the power module and the inductance from the power terminal to the capacitor. The long path of the power terminal and the equivalent series inductance (ESL) of the film capacitor significantly increase the total inductance. To eliminate the influence of this part, this paper proposes a capacitor direct connection (CDC) structure. The CDC structure mounts decoupling capacitors close to the position where the terminals protrude from the power module. The main body of the CDC structure is directly connected to the power terminals using its lower surface. The capacitors are arranged on the upper surface. The electrical connections within the upper and lower surfaces of the CDC structure rely on a large number of vias. The parasitic inductance outside of the power module is decreased to 1.1 nH by using the CDC structure in simulation, resulting in a low-inductance power loop within 5 nH.
A 1 200 V/600 A prototype of the proposed power module has been constructed and tested. The experimental results demonstrate that the power loop inductance of the prototype SiC power module based on the integral Cu clip bonding is 4.53 nH, 44.6% lower than that of the conventional layout. The inductance of the commutation loop is measured as 5.87 nH. The proposed power module packaging method is conducive to reducing the voltage overshoot and loss when using silicon carbide devices, thereby improving the efficiency of the converter. It can also enable the SiC devices to operate closer to their rated conditions and fully utilize their excellent performance.
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Received: 24 January 2025
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2025, Vol. 40 
