基于功率循环实验的不同栅极结构SiC MOSFET失效机理对比分析

doi:10.19595/j.cnki.1000-6753.tces.251479

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Abstract The fatigue failure of silicon carbide-based metal-oxide-semiconductor field-effect transistor（SiC MOSFET）caused by strong electro-thermal stresses poses a significant challenge to the reliability of traction converters. However, the effects of different gate structures（e.g., planar-gate and trench-gate）are rarely considered in many methods, which may lead to inaccurate predictions of remaining useful lifetime. This paper analyzes the failure mechanisms and the remaining useful lifetime prediction of SiC MOSFETs with different gate structures using power cycling tests（PCTs).
The impact of process variations in gate structure on junction temperature（T_j）calibration is investigated. Using the temperature-sensitive electrical parameter（TSEP）calibration method and computer-aided design（TCAD）simulations, it is shown that trench-gate SiC MOSFETs exhibit notable process variations that degrade calibration accuracy at low gate-off voltages. Simulation results indicate that an insufficient negative gate voltage fails to fully close the channel, causing part of the measurement current to flow through the channel rather than through the body diode. Therefore, a sufficient negative gate voltage（V_gs=-10 V）is determined to ensure the channel is fully closed, thereby guaranteeing the accuracy of T_j monitoring during PCTs.
Then, the degradation characteristics of the static and dynamic parameters are analyzed using the PCTs. For the saturation voltage drop V_ds, a planar-gate SiC MOSFET exhibits a typical three-stage aging trajectory: slow decline, stepped increase, and oscillation. In contrast, trench-gate SiC MOSFETs skip the stepped increase stage, directly entering oscillation and vertical rise. Such behavior stems from the vertical current path in trench structures. Failure of a single bond wire causes a sharp increase in current density and thermal stress in the remaining wires, triggering a cascade failure. Regarding the threshold voltage V_th, planar-gate SiC MOSFETs show a continuous negative drift, primarily dominated by interface-state charge Q_it. However, trench-gate SiC MOSFETs show an initial negative shift followed by a positive reversal due to the high electric field at the trench corners, which promotes the generation of gate-oxide trap Q_ot and acceptor-type interface states that eventually outweigh the initial negative drift. In dynamic parameters, planar and trench-gate SiC MOSFETs show opposing trends. The turn-on delay time t_d.on and rise time t_r decrease for planar-gate SiC MOSFET due to negative V_th drift, but increase for trench gate SiC MOSFET from positive V_th offset. Additionally, both structures exhibit increased switching losses（E_on, E_off）as package degradation raises the on-state resistance.
Furthermore, the mechanisms of competitive failure are elucidated using finite element analysis（FEA). In a planar-gate SiC MOSFET, the uniform electric-field distribution suppresses gate-oxide degradation, making bond-wire fatigue the dominant failure mode. Trench-gate SiC MOSFET exhibits a synergistic degradation mechanism. As a result, chip degradation actively promotes package failure.
Finally, the remaining useful lifetime of the two gate structures is compared using Weibull distribution fitting based on PCTs. The results suggest that the trench-gate SiC MOSFET exhibits a longer fatigue life than that of the planar-gate SiC MOSFET. The main reason is that the vertical trench structure facilitates heat conduction through the substrate, effectively reducing the junction temperature in the channel region. In contrast, the planar structure tends to accumulate heat near the surface.

Key words： SiC MOSFET different gate structures power cycling tests failure mechanism analysis remaining useful lifetime prediction

Received: 25 August 2025

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TM921.2

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	Jing Debao
	Wang Huimin
	Xu Zhiliang
	Zhao Jinshan
	Ge Xinglai

Cite this article:

Jing Debao,Wang Huimin,Xu Zhiliang等. Failure Mechanism Analysis of SiC MOSFET with Different Gate Structures Based on Power Cycling Tests[J]. Transactions of China Electrotechnical Society, 2026, 41(16): 5505-5520.

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https://dgjsxb.ces-transaction.com/EN/10.19595/j.cnki.1000-6753.tces.251479 OR https://dgjsxb.ces-transaction.com/EN/Y2026/V41/I16/5505

[1] Yıldırım D, Akşit M H, Yolaçan C, et al.Full-scale physical simulator of all SiC traction motor drive with onboard supercapacitor ESS for light-rail public transportation[J]. IEEE Transactions on Industrial Electronics, 2020, 67(8): 6290-6301.
[2] 文阳, 杨媛, 宁红英, 等. SiC MOSFET短路保护技术综述[J]. 电工技术学报, 2022, 37(10): 2538-2548.
Wen Yang, Yang Yuan, Ning Hongying, et al.Review on short-circuit protection technology of SiC MOSFET[J]. Transactions of China Electrotechnical Society, 2022, 37(10): 2538-2548.
[3] Wang Pengkai, Chen Yuan, Zhu Xinyu, et al.Failure mechanism analysis of 1.2 kV SiC MOSFETs under low-temperature storage, power cycling, and short-circuit interactions[J]. IEEE Journal of Emerging and Selected Topics in Power Electronics, 2024, 12(5): 4562-4572.
[4] 胡震, 崔曼, 吴晓华, 等. 功率器件结温主动控制及优化策略[J]. 电工技术学报, 2024, 39(18): 5732-5741.
Hu Zhen, Cui Man, Wu Xiaohua, et al.Active control and optimization strategy of junction temperature for power devices[J]. Transactions of China Electro-technical Society, 2024, 39(18): 5732-5741.
[5] Zhao Shengjun, An Tong, Qin Fei.Research on machine learning-assisted numerical simulation methods for IGBT module bonded interface fatigue damage[J]. IEEE Journal of Emerging and Selected Topics in Power Electronics, 2025, 13(3): 3259-3272.
[6] Zhu Mengyu, Pei Yunqing, Yang Fengtao, et al.An analytical switching loss model for SiC MOSFET considering temperature-dependent reverse recovery over an extremely wide high-temperature range[J]. IEEE Transactions on Power Electronics, 2024, 39(6): 7029-7044.
[7] Ge Xinglai, Chen Ken, Wang Huimin, et al.Failure mechanism investigations of bond wires lifting-off and die-attach solder aging considering the thermal coupling effects[J]. IEEE Transactions on Power Electronics, 2025, 40(1): 2042-2056.
[8] Shi Yidian, Chen Yuan, Zhu Wenhui, et al.Degra-dation mechanisms of SiC MOSFET power module with Cu-Cu die top interconnects under power cycling stress[J]. IEEE Journal of Emerging and Selected Topics in Power Electronics, 2024, 12(4): 3629-3636.
[9] 张经纬, 邓二平, 赵志斌, 等. 压接型IGBT器件单芯片子模组疲劳失效的仿真[J]. 电工技术学报, 2018, 33(18): 4277-4285.
Zhang Jingwei, Deng Erping, Zhao Zhibin, et al.Simulation on fatigue failure of single IGBT chip module of press-pack IGBTs[J]. Transactions of China Electrotechnical Society, 2018, 33(18): 4277-4285.
[10] 常桂钦, 罗海辉, 方超, 等. 散热底板对IGBT模块功率循环老化寿命的影响[J]. 电工技术学报, 2024, 39(8): 2485-2495.
Chang Guiqin, Luo Haihui, Fang Chao, et al.Influence of heat dissipation baseplate on power cycling lifetime of IGBT modules[J]. Transactions of China Electrotechnical Society, 2024, 39(8): 2485-2495.
[11] Wang Yanhao, Deng Erping, Wu Lixin, et al.Advanced power cycling test integrated with voltage, current, temperature, and humidity stress[J]. IEEE Trans-actions on Power Electronics, 2023, 38(6): 7685-7696.
[12] Zhang Zheng, Chen Chuantong, Suetake A, et al.Online condition monitoring of solder fatigue in a clip-bonding SiC MOSFET power assembly via acoustic emission technique[J]. IEEE Transactions on Power Electronics, 2023, 38(2): 1468-1478.
[13] 陈杰, 邓二平, 赵子轩, 等. 不同老化试验方法下SiC MOSFET失效机理分析[J]. 电工技术学报, 2020, 35(24): 5105-5114.
Chen Jie, Deng Erping, Zhao Zixuan, et al.Failure mechanism analysis of SiC MOSFET under different aging test methods[J]. Transactions of China Elec-trotechnical Society, 2020, 35(24): 5105-5114.
[14] Shi Yidian, Chen Yuan, Peng Cheng, et al.Com-petitive failures decoupling and mechanisms analysis of SiC MOSFET module under power cycling stress[J]. IEEE Journal of Emerging and Selected Topics in Power Electronics, 2023, 11(6): 5877-5888.
[15] 张浩然, 蔡雨萌, 孙鹏, 等. 脉冲电流应力下SiC MOSFET体二极管双极退化评估方法与退化特性[J]. 电工技术学报, 2025, 40(22): 7263-7275.
Zhang Haoran, Cai Yumeng, Sun Peng, et al.Degradation of SiC MOSFET body diode under pulse current stress[J]. Transactions of China Electro-technical Society, 2025, 40(22): 7263-7275.
[16] Long Yangtao, Chen Yuan, Wang Pengkai, et al.A novel insight into the mechanism of bipolar degra-dation in 4H-SiC MOSFET[J]. IEEE Electron Device Letters, 2025, 46(3): 464-467.
[17] Yang Xiaodong, Chen Y Q, Hou Bo, et al.Degradation behavior and defect analysis for SiC power MOSFETs based on low-frequency noise under repetitive power-cycling stress[J]. IEEE Transactions on Electron Devices, 2021, 68(2): 666-671.
[18] Kempiak C, Lindemann A.A method for the measurement of the threshold-voltage shift of SiC MOSFETs during power cycling tests[J]. IEEE Transactions on Power Electronics, 2021, 36(6): 6203-6207.
[19] 顾殿杰, 谢露红, 邓二平, 等. 考虑阈值电压漂移的SiC MOSFET功率循环寿命修正技术[J]. 半导体技术, 2024, 49(11): 1008-1015.
Gu Dianjie, Xie Luhong, Deng Erping, et al.Power cycling lifetime correction technique for SiC MOSFET considering threshold voltage drift[J]. Semiconductor Technology, 2024, 49(11): 1008-1015.
[20] Chen Yuan, Rao Yunliang, Wang Mei, et al.Investi-gation of threshold voltage instability of SiC MOSFETs under different gate voltage sequences[J]. IEEE Transactions on Electron Devices, 2024, 71(4): 2536-2542.
[21] Wang Mei, Chen Yuan, He Zhiyuan, et al.Com-parative investigation on aging precursor and failure mechanism of commercial SiC MOSFETs under different power cycling conduction modes[J]. IEEE Transactions on Power Electronics, 2023, 38(6): 7142-7155.
[22] Peng Yingzhou, Wang Qian, Wang Haoran, et al.An on-line calibration method for TSEP-based junction temperature estimation[J]. IEEE Transactions on Industrial Electronics, 2022, 69(12): 13616-13624.
[23] 王惠民, 许智亮, 丁菊霞, 等. 基于开通集射极电压下降平台的功率器件结温监测方法[J]. 电工技术学报, 2024, 39(15): 4682-4696.
Wang Huimin, Xu Zhiliang, Ding Juxia, et al.A junction temperature monitoring method for power devices based on turn-on collector-emitter voltage drop platform[J]. Transactions of China Electro-technical Society, 2024, 39(15): 4682-4696.
[24] Liao Yinda, Xu Zhiliang, Wang Huimin, et al.Investigations of off-line calibration and consistency of SiC MOSFETs with different gate structures[C]//2024 IEEE 10th International Power Electronics and Motion Control Conference（IPEMC2024-ECCE Asia), Chengdu, China, 2024: 3939-3944.
[25] ECPE GuidelineAQG 324: Qualification of power modules for use in power electronics converter units（PCUs）in motor vehicles[S]. Nuremberg, Germany: ECPE Working Group, 2018.