基于改进三电平拓扑的SiC MOSFET串扰抑制电路设计

doi:10.19595/j.cnki.1000-6753.tces.251570

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Abstract Silicon carbide（SiC）MOSFETs are widely used in power electronic converters due to their advantages, such as high switching speed. However, high dv/dt and di/dt are prone to causing crosstalk in half-bridge circuits, leading to false turn-on or device damage. Existing crosstalk suppression methods have limitations, including reduced switching speed, complex control, or one-sided suppression. Therefore, this paper proposes an improved crosstalk suppression drive circuit. Building on the three-level circuit topology, the scheme introduces an auxiliary low-impedance branch composed of an N-channel MOSFET in series with an auxiliary capacitor. Because of its intelligent self-driving capability, the branch requires no additional independent control signals and operates automatically only when the power switch is off, thereby providing an efficient bypass path for the Miller current that causes forward crosstalk. Simultaneously, because this branch effectively manages forward crosstalk, the turn-off negative voltage can be reduced. This elevation significantly reduces conduction loss across the gate resistor during the intermediate-level clamping interval, achieving an optimal balance between loss and suppression performance.
This paper begins with an in-depth analysis of the intrinsic mechanism of crosstalk generation in half-bridge circuits, detailing the paths of displacement current and their impact on the gate-source voltage during different switching transients. The operational principles of the proposed circuit throughout the entire switching cycle are provided using a stage-by-stage modal analysis. The study also offers design guidelines and a theoretical basis for key components. For instance, the value of the auxiliary capacitor must balance suppression effectiveness against its impact on switching characteristics, while the delay circuit's time constant must ensure that the clamping function activates within a safe timing window.
Finally, experimental validation was conducted using a double-pulse test platform. The results demonstrate that, compared to conventional drive circuits and traditional three-level circuits, the proposed improved circuit maintains comparable switching speed and losses while exhibiting superior performance in suppressing the forward crosstalk voltage spike. Additionally, it effectively reduces gate resistor losses. This solution addresses the performance trade-off, providing a practical and efficient approach to enhance the operational reliability of SiC MOSFETs in high-frequency applications.

Key words： SiC MOSFET crosstalk suppression drive circuit double-pulse test

Received: 09 September 2025

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TM46

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	Geng Yuyu
	Gou Xinyi
	Qu Changqi

Cite this article:

Geng Yuyu,Gou Xinyi,Qu Changqi. Design of SiC MOSFET Crosstalk Suppression Based on Improved Three-Level Topology[J]. Transactions of China Electrotechnical Society, 2026, 41(16): 5495-5504.

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https://dgjsxb.ces-transaction.com/EN/10.19595/j.cnki.1000-6753.tces.251570 OR https://dgjsxb.ces-transaction.com/EN/Y2026/V41/I16/5495

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