SiC/Si混合开关时间延迟及其信号调制方法

doi:10.19595/j.cnki.1000-6753.tces.240254

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Abstract Silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs) are increasingly preferred over Silicon (Si) insulated-gate bipolar transistors (IGBTs) due to their superior switching capabilities and high temperature withstand. Nonetheless, Si IGBTs maintain their position as the primary power devices in industrial settings, attributed to their greater durability and reduced on-resistance when dealing with high currents. However, the limited switching frequency of IGBTs impedes the advancement of power electronic converters, as the lingering currents during the off-transition phase lead to elevated switching losses. A hybrid SiC/Si switch (HyS) offers a balanced solution, optimizing cost and switching performance. Typical SiC/Si HyS control methods involve deactivating Si IGBTs sooner and reactivating them after SiC MOSFETs. The minimum conduction strategy for SiC MOSFETs within the SiC/Si HyS configuration ensures that SiC MOSFETs operate exclusively during the Si IGBTs’ switching intervals, which contributes to minimizing the expenses associated with SiC MOSFETs and the required chip space.
Since SiC MOSFET is activated twice during the switching transients of Si IGBT, the minimum SiC MOSFET conduction mode has two more controllable time scales than the common mode of SiC/Si HyS. By dissecting each sub-stage, the loss characteristics of the minimum SiC conduction mode are quantitatively analyzed. A visual relationship regarding the time scale and load current on the conduction loss is provided in a two-level sinusoidal inverter. At low-current conditions, the output characteristic of the Si IGBT is nonlinear, resulting in increased time scales that help to reduce the conduction loss.
A signal modulation circuit is proposed to conveniently generate the control signal for the minimum SiC MOSFET conduction HyS. The proposed circuit comprises one OR gate (Q₄) and three D flip-flops (Q₁~Q₃). The time delay is generated by adjusting the input signal rate with the RC buffer circuit. The rising edge of s_{O_on} and s_{O_off} generates the driving signal for Si IGBT. The pulse of s_{_drive} may be narrower than s_{O_on}or s_{O_off}, resulting in overlapping s_{O_on}and s_{O_off}. Consequently, s_I fails to be pulled down by the rising edge of s_{O_off}. Therefore, a NAND gate Q₅ is added to reset Q₃ when an overlapping signal occurs.
A simple signal modulation circuit is proposed for the minimum SiC MOSFET conduction mode of SiC/Si HyS to generate the corresponding driving signals for SiC MOSFET and Si IGBT. The four-time scales of the minimum SiC MOSFET conduction mode can be flexibly adjusted by adopting the calculated values of the RC buffer circuit. The loss characteristics of the minish SiC MOSFET conduction mode of SiC/Si HyS are described quantitatively. Subsequently, the paper introduces the operation principle and functional relationship of the RC buffer circuit. The relationship between the time scale and RC values is validated using the signal modulation circuit prototype. Combined with the signal modulation circuit and a double-pulse test circuit, the effect of the time scale of the minimum SiC conduction mode on the loss distribution of the SiC/Si HyS structure is verified. The proposed signal modulation circuit has good dynamic performance and stability in a 1.5 kW two-level inverter under the unipolar frequency-doubling modulation control mode. Furthermore, the experimental results show that SiC/Si HyS achieves better efficiency and temperature-escalating performance.

Key words： SiC MOSFET Si IGBT hybrid switch switching loss signal modulation

Received: 08 February 2024

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TM92

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	Ding Sibao
	Wang Panbao
	Wang Wei
	Xu Dianguo

Cite this article:

Ding Sibao,Wang Panbao,Wang Wei等. Analysis of SiC/Si HyS Loss Characteristics and Its Driving Signal Modulation Circuit[J]. Transactions of China Electrotechnical Society, 2025, 40(4): 1129-1144.

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https://dgjsxb.ces-transaction.com/EN/10.19595/j.cnki.1000-6753.tces.240254 OR https://dgjsxb.ces-transaction.com/EN/Y2025/V40/I4/1129

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