一种综合性能优化的两电平并联类交错一体化空间矢量调制策略

doi:10.19595/j.cnki.1000-6753.tces.250071

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Abstract Paralleling two three-phase inverters is a straightforward approach to expanding system capacity in high-power power electronics. Interleaved paralleling with carrier phase shift can cancel output current ripples of two inverters, significantly reducing the total harmonic distortion (THD) of grid-connected current and optimizing power quality. However, conventional interleaved systems typically adopt two-level space vector modulation (SVM), which is limited by insufficient vector degrees of freedom and struggles to meet multiple objectives such as common-mode voltage suppression, zero-sequence circulating current optimization, and switching loss reduction. Practical implementations often face issues, including common-mode voltage peaks reaching 1/2 of the DC bus voltage and zero-sequence circulating current Root Mean Square value exceeding the rated current, severely degrading system efficiency and reliability.
This paper proposes a similarly interleaved integrated space vector modulation (SISVM) strategy. By leveraging the advantages of vector degrees of freedom, a selection method for three-level vector sequences was established. The method incorporates three key innovations: (1) A multi-objective constrained vector selection framework is established with constraints including the feasibility of interleaved pulse generation, zero-sequence circulating current suppression, common-mode voltage reduction, and efficiency improvement. (2) The first large sector is re-divided into six sub-sectors, and the equivalent three-level vector sequences are accurately screened out with small zero-sequence circulation and low switching losses within each sub-sector. (3) A carrier- phase-shifted equivalent three-level space vector modulation technique is adopted to break through the vector degree-of-freedom limitation of two-level space vector modulation, expanding the degrees of freedom of interleaved paralleling.
First, an equivalent three-level system model of paralleled inverters was constructed. This model was used to investigate the effects of different vector sequences on common-mode voltage, zero-sequence circulating current, output current ripple, and switching losses. Accordingly, appropriate vector sequences were selected to optimize performance in each sub-sector. Then, quantitative calculation methods for output current ripple and zero-sequence circulating current in the two-phase stationary coordinate system were presented. The SISVM strategy can reduce zero-sequence circulating current and switching losses more effectively than the conventional TLSVM strategy, particularly under medium-to-high modulation indices.
Finally, a parallel system of two 3 kW inverters was built using a DSP+Starsim platform. Comparative experiments were carried out on four modulation strategies: ISVM, AZVPWM, TLSVM, and SISVM. Under different modulation ratios, performance metrics such as common-mode voltage, zero-sequence circulating current, output current THD, system efficiency, and program resource utilization were compared. Results showed that the common-mode voltage can be suppressed within V_dc/6 by the SISVM strategy. Without an additional increase in output current harmonics and hardware resources, the zero-sequence circulating current and switching losses in interleaved parallel modulation can be further reduced by the SISVM strategy. The effectiveness of the SISVM modulation strategy in terms of zero-sequence circulating current and switching losses is further demonstrated. The system's comprehensive performance can be optimized.

Key words： Interleaved parallel inverters common-mode voltage zero-sequence circulating current output current ripple switching loss similar interleaved integrated modulation

Received: 01 January 2025

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	Du Yan
	Liang Jing
	Cai Zhicheng
	Yang Xiangzhen
	Su Jianhui

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Du Yan,Liang Jing,Cai Zhicheng等. A Two-Level Parallel Similar-Interleaved Integrated Space Vector Modulation Strategy with Optimized Comprehensive[J]. Transactions of China Electrotechnical Society, 2026, 41(2): 622-634.

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