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| Analysis of Short-Circuit Withstand Time of SiC MOSFET and Short-Circuit Protection Based on di/dt-PMOS |
| Xie Jiaming1, Wei Jinxiao2, Wu Binbing1, Feng Hao1, Ran Li1 |
1. State Key Laboratory of Power Transmission Equipment Technology Chongqing University Chongqing 400044 China;
2. School of Electrical Engineering and Automation Hefei University of Technology Hefei 230000 China |
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Abstract The short-circuit tolerance of SiC MOSFETs is directly related to the heat generated during the short-circuit process, which is, in turn, directly related to the short-circuit current. Measuring short-circuit current characteristic curves under various parameters, including bus voltage, drive voltage, drive resistance, main circuit parasitic inductance, and gate threshold voltage, is essential. The impact of each parameter on the short-circuit current is analyzed to provide solutions for increasing the short-circuit withstand time (SCWT) of SiC MOSFETs. The drive voltage significantly influence the short-circuit current among these parameters, and lower gate voltage reduces the short-circuit current. Reducing the drive voltage can increase the SCWT of SiC MOSFETs. Additionally, the SCWT of SiC MOSFETs determines the maximum time for short-circuit protection actions. As a result, the settings of these different parameters directly affect the design of SiC MOSFET short-circuit protection circuits.
In traditional SiC MOSFET short-circuit protection strategies, the induced voltage generated by the parasitic inductance between the Kelvin source and power source, in conjunction with an RC filter, charges the capacitor (C) when the SiC MOSFET current changes, providing real-time feedback on the magnitude of the short-circuit current through the voltage across C. When the voltage across C exceeds a set value, the state of the SiC MOSFET is regarded as a short circuit. However, this traditional method has inconsistent short-circuit current thresholds for triggering short-circuit protection actions in hard switching faults (HSF) and fault under load (FUL), leading to the failure of short-circuit protection. Capacitor discharge is the main reason when the SiC MOSFET is normally turned on, resulting in a high short-circuit current threshold in the FUL state compared to the HSF state. Therefore, this paper proposes a short-circuit protection strategy based on di/dt-PMOS. This strategy places the PMOS's drain and source in series between the parasitic inductance and C. The unidirectional conductivity of the parasitic diode in the PMOS prevents the discharge of C when the SiC MOSFET is normally turned on, and the gate of the PMOS connecting to the SiC MOSFET's gate drive resets the discharge of C when the SiC MOSFET is turned off. It avoids complex discharge reset circuits for C and ensures the consistency of the short-circuit protection current threshold in both HSF and FUL states.
Practical measurements were conducted under different bus voltages and various initial junction temperatures. The proposed short-circuit protection strategy shows a minimum difference rate of only 3% in short circuits, while the traditional protection strategy exhibits a difference rate of 42%. The results demonstrate the effectiveness of the di/dt-PMOS-based short-circuit protection strategy for SiC MOSFETs.
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Received: 30 August 2024
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2025, Vol. 40 
