Low-Parasitic-Inductance SiC Power Modules with A Double-Sided Layout
Ma Haohao1,2, Yang Yuan1, Guo Sunyu1, Santiago Cobreces2, Li Yan3,4
1. School of Automation and Information Engineering Xi’an University of Technology Xi’an 710048 China; 2. Electronics Department University of Alcala Madrid 28805 Spain; 3. School of Mechanichal and Precision Instrument Engineering Xi’an University of Technology Xi’an 710048 China; 4. Xinjiang Institute of Engineering Urumqi 830023 China
Abstract：Silicon carbide (SiC) power modules are susceptible to parasitic inductance due to their high switching speed, with larger parasitic inductance exacerbating electrical stress and increasing switching losses. This paper proposes a novel SiC power module structure with a dual-sided layout, utilizing the structural characteristics of the direct bonded copper (DBC) substrate. By evenly distributing the power devices and interconnects on the upper and lower copper layers, the design achieves a symmetrical layout that maximizes mutual inductance effects and significantly reduces parasitic inductance. Additionally, the introduction of vias to create three-dimensional (3D) current paths effectively overcomes the limitations of traditional two-dimensional (2D) packaging, enhancing space utilization. Simulation and experimental results demonstrate that this structure significantly reduces parasitic inductance, optimizes dynamic characteristics, and improves power density. Moreover, a high-current surge test further verifies the reliability of the manufacturing process and the feasibility of large-scale production. The main contributions of this paper are as follows. (1) A dual-sided layout power module was proposed to minimize parasitic inductance in the power loop. The design evenly distributes power devices across the top and bottom copper layers of the DBC substrate, taking full advantage of the ceramic layer's insulating properties and mutual inductance cancellation effects. This approach effectively reduces parasitic inductance and the 50% substrate area, significantly increasing power density. (2) A via-based interconnection structure was presented, establishing electrical connectivity between the upper and lower bridge arms, effectively suppressing parasitic inductance and improving thermal stability. By creating vias in the DBC substrate, an electrical connection between the upper and lower copper layers is achieved, replacing the traditional bonding wire interconnection method. This further mitigates parasitic inductance. Additionally, the via design helps to relieve thermal stresses generated by thermal expansion, thus improving the module's thermal stability. (3) An innovative power terminal optimization scheme was presented to reduce parasitic inductance. A solution is introduced where the nuts are directly soldered onto the DBC substrate as power terminals. This design optimizes the external electrical connection path and reduces the parasitic inductance at the power terminals. (4) This paper comprehensively evaluates the proposed dual-sided layout power module through simulation using ANSYS Q3D, double-pulse testing, and extensive current surge testing. The Ansys Q3D simulation results indicate that, compared to traditional 2D bonding wire packaging, the dual-sided layout structure reduces parasitic inductance by 95%. Double-pulse testing demonstrates the advantages of this structure in dynamic characteristics, with a 37% reduction in voltage overshoot and a 14% decrease in switching losses compared to commercial modules. A high-current surge test was conducted to test the module's manufacturing process's reliability based on the first-class short circuit testing principle. The module, with a rated voltage of 1.2 kV and a current rating of 100 A, withstands a surge current of 1.135 kA at 900 V, demonstrating the module’s reliability under extreme conditions.
马浩浩, 杨媛, 郭孙毓, Santiago Cobreces, 李言. 基于双面布局的低寄生电感SiC功率模块[J]. 电工技术学报, 2025, 40(16): 5092-5105.
Ma Haohao, Yang Yuan, Guo Sunyu, Santiago Cobreces, Li Yan. Low-Parasitic-Inductance SiC Power Modules with A Double-Sided Layout. Transactions of China Electrotechnical Society, 2025, 40(16): 5092-5105.
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