For high power grid-connected converters, the switching frequency usually is low. Consequently, the negative effects enforced by the control delay and discretizing errors are heavy. However, traditional current control strategies generally ignored these negative effects and, hence, reducing the performance of the designed controller. Recently, some strategies were presented to compensate the control delay and the discretizing errors, but most of them suffered from the low dynamic response and the high sensitivity to the power grid harmonics. To address these issues, a current control strategy combining the bridge arm-side and the grid-side currents is designed directly in the discrete-time domain and pole-zero placement is used in synchronous coordinates. Meanwhile, a differentiator to the capacitor voltage is introduced to make estimation of the grid-side currents. Consequently, hardware complexity as well as the corresponding control cost is reduced.
Discrete-time model of the converter with LCL as output filter is built in synchronous coordinates, including the computational delay, firstly. Following that, the corresponding structure of the combining state-space control scheme is as follows: the harmonic control loop of the grid-side currents is constructed and combined with the fundamental current control loop on the bridge arm-side, which uses the full state-feedback control. And then, the integral controller is introduced for improved disturbance rejection and the reference-feedforward controller is designed to increase the reference-tracking dynamic performance. Consequently, the closed-loop transfer function of the system is obtained based on the discrete-time model and the control scheme, and then the state feedback function matrix and the feedforward module are optimized based on the pole-zero placement. Finally, a differentiator is introduced to make estimation of the grid-side currents, reducing the hardware cost.
Experiment results based on a hardware-in-loop simulator show: the response time of the bridge arm-side currents to a 1000A step-up change is about 4.5ms; the recovery time of the bridge arm-side currents facing a grid-voltage dip of 0.4 p.u.is about 10ms; and the total harmonic distortion of the grid-side currents is 2.28%, below the 5% limit given in standards, in the circumstances of 6% fifth and seventh harmonic components appearing in the grid voltage. Finally, to verify the robustness of the proposed strategy to the parameter deviations, the actual system parameters are deviated artificially from their nominal values. The experimental results show that the proposed strategy can operate satisfactorily in the range of ±40% parameter deviations and the influence of the parameter deviations is low.
The following conclusions can be drawn from the experiment results: (1) compared with the typical discrete-time state-space control strategy, the proposed strategy keeps the same great dynamic performance but achieves an improved capability of rejecting the grid harmonic-disturbance. (2) the proposed control strategy simplifies the design complexity based on the direct pole-zero placement and increases the degrees of freedom based on the combining design of fundamental current and harmonic control loops. (3) the differentiator to the capacitor voltage is designed to get knowledge of grid-side currents without additional current sensors and the corresponding sampling circuit required, reducing the hardware complexity and the cost.
王旭, 杨淑英, 李典, 张兴. 大功率并网变流器离散域电流控制策略[J]. 电工技术学报, 0, (): 133-133.
Wang Xu, Yang Shuying, Li Dian, Zhang Xing. Discrete-time domain Current Control Strategy for High Power Grid-connected Converters. Transactions of China Electrotechnical Society, 0, (): 133-133.
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