高速SiC MOSFET开关特性的测试方法

doi:10.19595/j.cnki.1000-6753.tces.L70526

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Abstract In order to precisely test the switching performance of high speed SiC MOSFET, this paper will focus on the precise test method in the double pulse test platform. The effects of the parasitic inductors on the switching performance are illustrated by simulation, and the PCB layout is optimized to reduce the parasitic inductors. The tested results of two PCB layouts are compared. The effects of the parasitic capacitors in the flywheel diode and the load inductor on the turn-on switching performance are presented. The tested results by different passive voltage probes, different grounding connecting ways and different current test equipment are compared. The impacts of the phase delay on the turn-on and turn-off switching loss are presented. At last, the proper test points are shown clearly in this paper.

Key words： Test method, switching performance, high speed SiC MOSFET, parasitic parameters

Received: 20 August 2016 Published: 01 August 2017

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TM133

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	Articles by authors
	Liang Mei
	Li Yan
	Zheng Trillion Q
	Zhao Hongyan

Cite this article:

Liang Mei,Li Yan,Zheng Trillion Q等. Test Method for Switching Performance of High Speed SiC MOSFET[J]. Transactions of China Electrotechnical Society, 2017, 32(14): 87-95.

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https://dgjsxb.ces-transaction.com/EN/10.19595/j.cnki.1000-6753.tces.L70526 OR https://dgjsxb.ces-transaction.com/EN/Y2017/V32/I14/87

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