全数字硬件化锁相环参数分析与设计

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Abstract The all-digital full-hardware implementation based on field-programmable gate array (FPGA) or application specific integrated circuits(ASIC) has the advantages of high parallelism and full-customer, so the optimization of performance index and cost of implementation is necessary to achieve the specified performance consuming the least resources. The performance indexes of all- digital full-hardware phase-locked loop(PLL) which can not be described in the s domain completely are derived in the z domain firstly, such as peak time, overshoot and setting time, and then this paper points out that one-step-delay in feedback causes the performance degradation, which is studied followed. Simulation and experimental results show that there is no obvious degradation of peak time, but the contour of setting time and overshoot are changed clearly, which strengthen the coupling of the integral and proportional coefficient.

Key words： Phase-locked loop all-digital full-hardware field-programmable gate array(FPGA)

Received: 07 March 2014 Published: 14 April 2015

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TM315

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	Liu Yajing
	Fan Yu

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Liu Yajing,Fan Yu. Design and Analysis of All-Digital Full-Hardware Phase-Locked Loop[J]. Transactions of China Electrotechnical Society, 2015, 30(2): 172-179.

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http://dgjsxb.ces-transaction.com/EN/ OR http://dgjsxb.ces-transaction.com/EN/Y2015/V30/I2/172

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