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| A Digital Modulation Method for Dead-Time Compensation and Capacitor Voltage Balance in Diode Clamped Three-Level Inverter |
| Ning Jichao1, Ben Hongqi1, Wang Xuesong2, Meng Tao3 |
1. School of Electrical Engineering and Automation Harbin Institute of Technology Harbin 150001 China;
2. State Grid Harbin Power Supply Company Harbin 150000 China;
3. School of Mechanical and Electrical Engineering Heilongjiang University Harbin 150080 China |
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Abstract With the development of wide bandgap semiconductor devices, high power density can be achieved by high switching frequencies combined with diode-clamped three-level inverters (DCTLI) and wide bandgap semiconductor devices like gallium nitride (GaN) and silicon carbide (SiC). However, problems that are well solved at low switching frequencies may be difficult to solve at high switching frequencies.
In DCTLI, there are two main problems: the influence of dead time and the capacitor voltage balance. Dead time introduces harmonics into the output waveform, degrading the output waveform quality. Unbalanced capacitor voltages reduce converter reliability and even damage transistors. In addition, delay mismatches associated with dead time affect capacitor voltage balance. However, limited by computing power requirements, existing methods are challenging to achieve good results at high switching frequencies, and the additional sensors required are not conducive to realizing high power density.
Therefore, the effects of dead time on the output waveform and capacitor voltage balance are analyzed. Then, a digital modulation method without additional sensors is proposed for high switching frequencies. The resistor divider network introduces the output voltage information of the bridge. The driving signal is generated by making the count value of the output voltage of the bridge equal to the reference signal. Accordingly, the average value of the inverter bridge output waveform is forced to track the reference signal, so dead time effects are compensated directly in the modulator section. The capacitor voltage balance state is collected through the resistor voltage dividing network, and the balance state is accumulated through the counter. As a result, the modulator obtains the degree of capacitor voltage imbalance and modifies the reference signal to balance the capacitor voltage.
In addition, the effects of the quantization and sampling, the propagation delay of the digital isolator, and the finite sampling clock on the proposed method are analyzed. It is shown that these factors have little impact on the proposed method. Design criteria for the capacitor voltage balancing frequency division coefficient M are given based on trade-off considerations for capacitor voltage balancing speed and steady-state ripple.
Finally, the proposed method is compared with traditional dead time compensation and capacitor voltage balancing methods through simulations. The advantages and disadvantages of the proposed methods are summarized. The effectiveness of the proposed method is verified under different loads (resistive load, resistive step load, capacitive load, inductive load, and rectifier load) and different conditions (switching frequency, modulation ratio, dead-time delay mismatch, and dead time). Simulation and experiments show that the proposed method can effectively suppress the impact of dead time and maintain capacitor voltage balance, which is effective at high switching frequencies.
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Received: 16 August 2023
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2024, Vol. 39 
