Abstract Silicon carbide MOSFETs are of excellent performance and potentially replace traditional silicon IGBTs in high-power power converters. However, commercial silicon carbide power modules still employ the packaging technology of traditional silicon IGBT modules, limiting the excellent performances of silicon carbide semiconductors. In order to solve the above problem and take advantage of silicon carbide chips, many new packaging schemes for silicon carbide power modules have emerged in recent years, focusing on the electrical, thermal, and insulation challenges in the packaging of silicon carbide power modules. As for the electrical challenges, the parasitic inductance in commutation loops is widely concerned. The parasitic inductance on the conductors connects the chips to the external circuits in power modules, which can greatly affect the switching performance of silicon carbide MOSFETs, such as increasing voltage overshoot and arousing oscillations. Then the stress on the chip will be increased, and the switching losses may also be enlarged. Compared to Si IGBTs, SiC MOSFET-based power modules can switch faster, which presents more strict requirements for parasitic inductance. Therefore, new packaging structures are demanded to lower parasitic inductance. There are two ways. The first one is to reduce the self-parasitic inductance. In this aspect, the shapes of connection conductors are optimized. The ribbon bonding techniques, such as aluminum ribbons, copper ribbons, and aluminum-copper ribbons, aim to mitigate the parasitic inductance by increasing the cross-sectional areas. Accordingly, the self-parasitic inductance can be well reduced. Similar techniques include copper-clip connections and planar connections. The second way adopts loop mutual inductance to eliminate the overall parasitic inductance. By reducing the areas of commutation loops, the mutual inductance between conductors can be greatly increased, which can reduce self-parasitic inductance and then reduce the overall parasitic inductance. As for the thermal challenges, there are two problems. On the one hand, the overall package size must be reduced to minimize parasitic inductance, making the heat dissipation issues more severe. Many methods have been proposed to enhance heat dissipation in limited spaces. The optimization of heat dissipation is mainly attributed to two technical routes: shortening the heat transfer paths and increasing the heat transfer areas. To shorten heat transfer paths, some modules remove the baseplates and even directly solder the substrates on the heatsinks. The key to improving equivalent heat dissipation areas on the bottom surface of the chip is to achieve a uniform temperature distribution. Some research has realized this goal by changing the material of the copper layer under the chip or integrating heat pipes into baseplates or substrates. In addition, double-side cooling structures can be utilized to directly increase equivalent heat transfer areas. On the other hand, the ability of silicon carbide chips to operate at high temperatures is limited by the shortcomings of traditional packaging materials. The reliability of current high-temperature-resistant packaging materials requires further verification under a wide range of temperature cycles. As for insulation challenges, high voltage variation slews and high electric field strength in power modules place higher demands on the insulation performance of the package. Methods to enhance insulation performances in compact spaces of power modules have been reported, such as employing stacked substrates, optimizing three-phase point structures, and adopting functional gradient materials. The packaging technology of SiC power modules is reviewed from aspects of lowering parasitic inductance, enhancing thermal performance, and improving insulation performance. Rules for optimizing the performance of SiC power modules on the three aspects are summarized.
Wang Laili,Zhao Cheng,Zhang Tongyu等. Review of Packaging Technology for Silicon Carbide Power Modules[J]. Transactions of China Electrotechnical Society, 2023, 38(18): 4947-4962.
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