一种消除反馈延迟的全数字锁相环

doi:10.19595/j.cnki.1000-6753.tces.170367

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Abstract The feedback unit delay in conventional digital PLL causes adverse effects to system steady-state and dynamic performance. Therefore, referred to ideal digital PLL without feedback delay, an improved digital PLL was proposed utilizing the present and previous outputs of PLL to calculate the ideal output. The proposed novel PLL with merely two additional multipliers can improve the system stability dramatically. Moreover, the performance indexes designed in s domain can be implemented strictly in z domain, to overcome the performance degeneration in conventional PLL. Simulation and experimental results show that both step response and frequency response of the novel digital PLL accord with those of the ideal digital PLL. The novel digital PLL improves the performance significantly with low computational burden, which implies its considerable practical value.

Key words： Phase-locked loop (PLL) feedback unit delay delay compensation dynamic performance

Received: 01 April 2017 Published: 30 October 2017

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TM46

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	Articles by authors
	Sun Gaoyang
	Liu Yajing
	Li Bingge
	Zhu Yulong
	Fan Yu

Cite this article:

Sun Gaoyang,Liu Yajing,Li Bingge等. An All-Digital Phase-Locked Loop with Compensating Feedback Unit Delay[J]. Transactions of China Electrotechnical Society, 2017, 32(20): 171-178.

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https://dgjsxb.ces-transaction.com/EN/10.19595/j.cnki.1000-6753.tces.170367 OR https://dgjsxb.ces-transaction.com/EN/Y2017/V32/I20/171

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