全数字硬件化正交锁相环建模与分析

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Abstract The word-length modeling method for all-digital full-hardware (ADFH) quadrature phase-locked loop (QPLL) that is implemented with field programmable gate array (FPGA) or application specific integrated circuits (ASICs) is proposed for word-length optimization brought by full-customized FPGA/ASIC. The integer word-length model of the coefficients and the internal variables are built using stability criterion and convolution respectively. Then,the coefficient and internal variable fraction word-length model are constructed in accordance with the system sensitivity theory and norm2 separately. So the ADFH QPLL can be designed using the proposed method with predefined coefficient precision parameter ε and variable precision parameter ζ. The method can effectively avoid overflow errors and finite-word-length effect with minimum cost. Simulation and experiment results verify the validity of the proposed model.

Key words： Quadrature phase-locked loop (QPLL) all-digital full-hardware (ADFH) word-length model finite-word-length effect

Received: 11 December 2014 Published: 08 September 2015

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TM315

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