离散周期对伺服系统用全数字硬件化锁相环的影响机理

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Abstract The digital control system based on field-programmable gate array(FPGA) or application specific integrated circuits(ASIC) has the advantages of full-hardware, parallelism, and flexibility, so it is a high-speed, high-performance solution of magnetic encoder-to-digital converter(MEDC) with phase- locked loop(PLL). But there are some problems such as determination of parameters-region, optimization of word-length etc, which have a close connection with discrete period. The delta operator is employed to discrete the continuous-time PLL system so as to do the stability analysis of discrete-time PLL system with one-step-delay firstly, so the integer word-length of coefficients are determined. And then, error source model and error propagations model based on L2-norm are established, and the effect of discrete period on fractional word-length of improved PLL is analysed, so the design method of fractional word-length is derived. The simulation and experimental results verify the correctness and effectiveness of proposed analysis.

Key words： Phase locked loop all-digital full-hardware servo system field-programmable gate array

Received: 03 July 2013 Published: 05 November 2014

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TM315

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	Liu Yajing
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Liu Yajing,Fan Yu. Effect of Discrete Period on All-Digital Full-Hardware Phase-Locked Loop Using in Servo System[J]. Transactions of China Electrotechnical Society, 2014, 29(9): 153-160.

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http://dgjsxb.ces-transaction.com/EN/ OR http://dgjsxb.ces-transaction.com/EN/Y2014/V29/I9/153

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