Abstract：This paper proposes a realization method of (Build In Self Test, BIST) technique of sequential circuits based on chaotic sequence. “0-1”Random sequences with the white noise characteristics which generate by chaotic logistic map model suite as digital circuits test pattern. Test response signature of chaotic sequence are obtained from the output response characteristic analysis of (Cyclic Redundancy Check, CRC) circuits. Studies have shown that the chaotic iterative sequence test pattern is not unique to impose order especially for sequential circuits, so the method presented in this paper fault detection rate is greater than that of M sequence and easy for realization of BIST, and suitable for large-scale FPGA and other programmable logic circuits automatic testing.
朱敏, 杨春玲. 基于混沌序列的时序数字电路BIST技术[J]. 电工技术学报, 2010, 25(6): 144-149.
Zhu Min, Yang Chunling. BIST Technique of Sequential Circuits Based on Chaotic Sequence. Transactions of China Electrotechnical Society, 2010, 25(6): 144-149.
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