Abstract：The word-length modeling method for all-digital full-hardware (ADFH) quadrature phase-locked loop (QPLL) that is implemented with field programmable gate array (FPGA) or application specific integrated circuits (ASICs) is proposed for word-length optimization brought by full-customized FPGA/ASIC. The integer word-length model of the coefficients and the internal variables are built using stability criterion and convolution respectively. Then,the coefficient and internal variable fraction word-length model are constructed in accordance with the system sensitivity theory and norm2 separately. So the ADFH QPLL can be designed using the proposed method with predefined coefficient precision parameter ε and variable precision parameter ζ. The method can effectively avoid overflow errors and finite-word-length effect with minimum cost. Simulation and experiment results verify the validity of the proposed model.
[1] 刘亚静,范瑜.全数字伺服电机轴角转换单元建模与分析[J].中国电机工程学报,2013,33(3):148-154. Liu Yajing,Fan Yu.Modeling and analysis of an all-digital magnetic encoder-to-digital converter for servo motors[J].Proceedings of the CSEE,2013,33(3):148-154. [2] 刘亚静,范瑜.离散周期对伺服系统用全数字硬件化锁相环的影响机理分析[J].电工技术学报,2014,29 (9):153-160. Liu Yajing,Fan Yu.Effect of discrete period on all-digital full-hardware phased locked loop using in servo system[J].Transactions of China Electrotechnical Society,2014,29(9):153-160. [3] 刘亚静.多轴电机控制的集成技术研究[D].哈尔滨:哈尔滨工业大学,2011. [4] Cmar R,Rijinders L,Schaumont P.A methodology and design environment for DSP ASIC fixed point refinement[C].Proceedings of automation and test in europe conference,Munich,Germany,1999:271-276. [5] Fang C F,Rutenbar R,Chen T.Fast,accurate static analysis for fixed-point finite-precision effects in DSP design[C].International conference on computer-aided design,San Jose,CA,2003:275-282. [6] Ozer E,Nisbet P,Gregg D.A stochasitic bitwidth estimation technique for compact and low-power custom processors[J].ACM Transactions on Embedded Computing Sysetm,2008,7(3):1-30. [7] Williamson D,Kadiman K.Optimal finite wordlength linear quadratic regulation[J].IEEE Transactions on Automatic Control,1989,34(12):1218-1228. [8] Wu J,Chen S,Li G,et al.An improved closed-loop stability related measure for finite-precision digital controller realizations[J].IEEE Transactions on Automatic Control,2001,46(7):1162-1166. [9] Li G,Gevers M.Optimal finite precision implement- ation of a state-estimate feedback controller[J].IEEE Transactions on Circuits and Systems,1990,37(12):1487-1498. [10]Cheng K Y,Tzou Y Y.Design of a sensorless commu- tation IC for BLDC motors[J].IEEE Transactions on Power Electronics,2003,18(6):1365-1375. [11]周兆勇,李铁才,高桥敏男.基于矢量控制的高性能交流电机速度伺服控制器的FPGA实现[J].中国电机工程学报,2004,24(5):168-173. Zhou Zhaoyong,Li Tiecai,Toshio Takahashi.FPGA implementation of the high-performance vector- controlled speed servo controller of AC drivers[J].Proceedings of the CSEE,2004,24(5):168-173. [12]Jung S L,Chang M Y,Jyang J Y.Design and implementation of an FPGA-based control IC for AC-voltage regulation[J].IEEE Transactions on Power Electronics,1999,14(3):522-532. [13]Naouar M W,Naassani A A,Monmasson E.FPGA-based predictive current controller for synchronous machine speed drive[J].IEEE Transactions on Power Electronics,2008,23(4):2115-2126. [14]Naouar M W,Monmasson E,Naassani A A.FPGA-based current controllers for AC machine drives—a review[J].IEEE Transactions on Industrial Electronics,2007,54(4):1907-1925. [15]Monmasson E,Cirstea M N.FPGA design methodology for industrial control systems—a review[J].IEEE Transactions on Industrial Electronics,2007,54(4):1824-1842.
2015, Vol. 30 
