Abstract：The paper proposes an all digital phase-locked-loop (ADPLL) with a ratio changeable divider. Compared to the conventional one, because of the divider with a changeable ratio, the proposed ADPLL features variable central frequency thus having a wide track-in range. A feed-forward control loop is also integrated into the proposed ADPLL to decrease the pull-in time. By employing the Proportional-Integral (PI) structure based loop filter, the output phase of the ADPLL has no static error and small output jittering. The performance and parameter dependency are analyzed based on the small signal model of the ADPLL in the paper. After that, the ADPLL is evaluated with the Quartus II based simulations and FPGA based experiments. The results show that the proposed ADPLL has a large track-in range, short pull-in time and high accuracy, and can be applied to the system with fast synchronization requirements, such as grid-connected power converters.
肖帅, 孙建波, 耿华, 吴舰. 基于FPGA实现的可变模全数字锁相环[J]. 电工技术学报, 2012, 27(4): 153-158.
Xiao Shuai, Sun Jianbo, Geng Hua, Wu Jian. FPGA Based Ratio Changeable All Digital Phase-Locked-Loop. Transactions of China Electrotechnical Society, 2012, 27(4): 153-158.
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